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Electrical Specifications Subject to Change
LTC3589 8-Output Regulator with Sequencing and I2C FEATURES
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DESCRIPTION
The LTC(R)3589 is a complete power management solution for ARM and ARM-based processors and advanced portable microprocessor systems. The device contains three synchronous step-down DC/DC converters for core, memory and SoC rails, a synchronous buck-boost regulator for I/O at 3.3V to 5V, and three 250mA LDO regulators for low noise analog supplies. An I2C serial port is used to control regulator enables, output voltage levels, dynamic voltage scaling and slew rate, operating modes and status reporting. Regulator start-up is sequenced by connecting regulator outputs to enable pins in the desired order or via the I2C port. System power-on, power-off and reset functions are controlled by pushbutton interface, pin inputs, or I2C interface. The LTC3589 supports i.MX, PXA and OMAP processors with eight independent rails at appropriate power levels, dynamic control and sequencing. Other features include interface signals such as the VSTB pin that toggles between programmed run and standby output voltages on up to four rails simultaneously. The device is available in a low profile 40-pin 6mm x 6mm exposed pad QFN package.
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks, Hot Swap and Bat-track are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Triple I2C Adjustable High Efficiency Step-Down Switching Regulators: 1.6A, 1A, 1A High Efficiency 1.2A Buck-Boost Switching Regulator Triple 250mA LDO Regulators Always Alive 25mA LDO Regulator Flexible Pin-Strap Sequencing Operation I2C and Independent Enable Control Pins Power Good and Reset Outputs Dynamic Voltage Scaling and Slew Rate Control Selectable 2.25MHz or 1.12MHz Switching Frequency Pushbutton ON/OFF Control with System Reset 10A Standby Current 40-Pin 6mm x 6mm x 0.75mm QFN
APPLICATIONS
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Handheld Instruments and Scanners Portable Industrial Devices Automotive Infotainment Portable Medical Devices High End Consumer Devices Multirail Systems Supports Freescale i.MX, Marvell PXA and Other Application Processors
TYPICAL APPLICATION
VRTC 1.2V AT 25mA MEMORY 0.9V TO 1.2V AT 250mA ANALOG 1.8V AT 250mA 1.8V, 2.5V, 2.8V, 3.3V AT 250mA VIN LDO1_STDBY
VIN 2.7V TO 5.5V
Start-Up Sequence
SW1 VCORE 0.6V TO 1.2V AT 1.6A I/O LDO2 LTC3589 SW2 VSRAM 0.9V TO 1.8V AT 1A VSOC 0.625V TO 1.25V AT 1A DDR MEMORY SW4AB SW4CD BB_OUT WAKE PBSTAT PGOOD GND RSTO
3589 TA01a
WAKE (1V/DIV) VSRAM ANALOG VSOC MEMORY VCORE I/O 3.3V AT 1.2A OR 5V AT 1A 500s/DIV
3589 TA01b
LDO3
SW3
LDO4 3 I 7 ENABLES
2C
FROM PROCESSOR
VSTB PWR_ON ON (PB)
HDD OR I/O
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LTC3589 TABLE OF CONTENTS
Features ............................................................................................................................ 1 Applications ....................................................................................................................... 1 Typical Application ............................................................................................................... 1 Description......................................................................................................................... 1 Absolute Maximum Ratings ..................................................................................................... 3 Pin Configuration ................................................................................................................. 3 Order Information ................................................................................................................. 3 Electrical Characteristics ........................................................................................................ 4 Typical Performance Characteristics .......................................................................................... 8 Pin Functions .....................................................................................................................12 Block Diagram....................................................................................................................14 Operation..........................................................................................................................15 Introduction .......................................................................................................................................................... 15 Always-On LDO..................................................................................................................................................... 16 250mA LDO Regulators ........................................................................................................................................ 16 Step-Down Switching Regulators ......................................................................................................................... 18 Buck-Boost Switching Regulator .......................................................................................................................... 22 Slewing DAC Reference Operation ........................................................................................................................ 26 Pushbutton Operation ........................................................................................................................................... 27 Enable and Power-On Sequencing ........................................................................................................................ 29 Fault Detection, Shutdown, and Reporting............................................................................................................ 30 I2C Operation ........................................................................................................................................................ 32 Thermal Considerations and Board Layout ........................................................................................................... 38 Applications Information .......................................................................................................40 Typical Application ..............................................................................................................42 Package Description ............................................................................................................43 Typical Application ..............................................................................................................44 Related Parts .....................................................................................................................44
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LTC3589 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 3)
SW1, SW2, SW3, SW4AB, SW4CD (Transients < 1ms, Duty Cycle < 1%) ......................................... -0.3V to 7V PVIN1, PVIN2, PVIN3, PVIN4 ............... -0.3V to VIN + 0.3V VIN_LDO2, VIN_LDO34..........................-0.3V to VIN + 0.3V VIN, DVDD ..................................................... -0.3V to 6V LDO1_STBY, LDO1_FB, BUCK1_FB, BUCK2_FB, BUCK3_FB, BB_FB, BB_OUT, LDO2, LDO2_FB,LDO3, LDO4, PGOOD,
VSTB, EN1, EN2, EN3, EN4, EN_LDO2, EN_LDO34, ON, PBSTAT, WAKE, RSTO, PWR_ON, IRQ, ....... -0.3V to 6V SDA, SCL .....................................-0.3V to DVDD to 0.3V Operating Junction Temperature Range (Note 2).................................................. -40C to 150C Storage Temperature Range .................. -65C to 150C
PIN CONFIGURATION
TOP VIEW LDO1_STBY BUCK1_FB BUCK3_FB BUCK2_FB LDO2_FB LDO1_FB BB_FB
DVDD SW4CD
40 39 38 37 36 35 34 33 32 31 VIN_LDO2 1 LDO2 2 LDO3 3 LDO4 4 VIN_LD34 5 PVIN1 6 SW1 7 RSTO 8 EN_LDO2 9 EN1 10 11 12 13 14 15 16 17 18 19 20 PVIN4 BB_OUT IRQ EN_LDO34 PWR_ON EN2 SW4AB EN3 EN4 41 GND 30 SCL 29 PGOOD 28 VSTB 27 PVIN3 26 SW3 25 SW2 24 PVIN2 23 WAKE 22 PBSTAT 21 ON
UJ PACKAGE 40-LEAD (6mm x 6mm) PLASTIC QFN TJMAX = 125C, JA = 34C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC3589EUJ#PBF LTC3589IUJ#PBF LTC3589HUJ#PBF TAPE AND REEL LTC3589EUJ#TRPBF LTC3589IUJ#TRPBF LTC3589HUJ#TRPBF PART MARKING* 3589 3589 3589 PACKAGE DESCRIPTION 40-Lead (6mm x 6mm) Plastic QFN 40-Lead (6mm x 6mm) Plastic QFN 40-Lead (6mm x 6mm) Plastic QFN TEMPERATURE RANGE -40C to 125C -40C to 125C -40C to 150C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3589p
SDA
VIN
3
LTC3589 ELECTRICAL CHARACTERISTICS
SYMBOL VIN IVINLDO1 fOSC IVIN PARAMETER Operating Input Supply Voltage, VIN VIN Quiescent Current Oscillator Frequency Pulse-Skipping Mode VIN Quiescent Current Per Buck Burst Mode (R) VIN Quiescent Current Per Buck Feedback Pin Input Current Maximum Duty Cycle SW Pull-Down Resistance Soft-Start Rate Maximum Feedback Voltage Feedback LSB Step Size Minimum Feedback Voltage BxDTV1 = BxDTV2 = 00000, VIN = 2.7V to 5.5V
l
The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_LDO2 = VIN_LDO34 = DVDD = 3.8V. All regulators disabled unless otherwise noted.
CONDITIONS
l
MIN 2.7
l l l l
TYP 10
MAX 5.5 17 2.6 TBD 40 0.1
UNITS V A MHz A A A % V/ms
All Enables = 0V
1.9
2.25 135 27
Step Down Switching Regulators 1, 2, and 3 VFB = 0.85V (Note 5)
IFB DX RSW tSS VFB(MAX) VFB(LSB) VFB(MIN)
V FB = 0.8V VFB = 0V Regulators Disabled (Note 6) BxDTV1 = BxDTV2 = 11111, VIN = 2.7V to 5.5V
l
-0.1 100 2000 2 0.735 0.75 12.5 0.351 0.3625
0.765
V mV
0.374
V
1.6A Step Down Switching Regulator 1 (Buck 1) ILIM1 RP1 RN1 ILIM2, 3 RP2, 3 RN2, 3 IVIN VBB_FB VOUTBB ILIM4 IPEAK4 ILIMR4 IZERO4 RP4 RN4 ROUT4 tSS IFB Peak PMOS Current Limit SW1 RDS(ON) of PMOS1 RDS(ON) of NMOS1 Peak PMOS Current Limit SW2 RDS(ON) of PMOS3 RDS(ON) of NMOS3 PWM Mode VIN Quiescent Current Burst Mode VIN Quiescent Current Feedback Voltage Output Voltage Range Peak PMOS Current Limit SW4AB Forward Burst Current Limit (Switch A) Reverse Current Limit (Switch D) Reverse Burst Current Limit (Switch D) RDS(ON) of Switch A and Switch D RDS(ON) of Switch B and Switch C BB_OUT Pull-Down Resistance Soft-Start Rate Feedback Pin Input Current Burst Mode Operation ISW4AB = ISW4CD = 100mA ISW4AB = ISW4CD = -100mA Regulator Disabled (Note 6) V FB = 0.85V -0.1 Burst Mode Operation
l l
2.2
2.7 180 110
A m m A m m 130 19 A A V V A mA mA mA m m V/ms 0.1 A
ISW1 = 100mA ISW1 = 100mA
l
1.0A Step Down Switching Regulators 2 and 3 1.5 1.9 250 130 VBB_FB = 0.85V VIN = 2.7V to 5.5V, VOUT = 5.5V
l l l
1.2A Buck-Boost Switching Regulator 4 (Buck-Boost)
0.776 1.8 2.5
0.8 2.7 500 800 0 160 110 2000 2
0.824 5.0
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LTC3589 ELECTRICAL CHARACTERISTICS
SYMBOL tLDO_SS RLDO_PD PARAMETER Soft-Start Time LDO2, LDO3, LDO4 Output Pull-Down Resistance LDO2, LDO3, LDO4 LDO1 Feedback Voltage LDO1 Line Regulation LDO1 Load Regulation ILDO1 ILDO1_SC VDROP1 ILDO1_FB VIN_LDO2 IVIN_LDO2 IVIN VFB2(MAX) VFB2(LSB) VFB2(MIN) Available Output Current Short Circuit Output Current Limit Dropout Voltage (Note 4) LDO1_FB Input Current VIN_LDO2 Input Voltage Range VIN_LDO2 Quiescent Current VIN_LDO2 Shutdown Current VIN Quiescent Current LDO2 Maximum Feedback Voltage LDO2 Feedback LSB Step Size LDO2 Minimum Feedback Voltage L2DTV1 = L2DTV2 = 00000 VIN_LDO2 = VIN = 2.7V to 5.5V, ILDO2 = 1mA ILDO2 =1mA, VINLDO2 = 2.7V to 5.5V ILDO2 = 1mA to 250mA
l l
The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_LDO2 = VIN_LDO34 = DVDD = 3.8V. All regulators disabled unless otherwise noted.
CONDITIONS MIN TYP 100 LDO Disabled 2000 MAX UNITS s
LDO Regulators
Always-On Regulator (LDO1_STDBY) VLDO1_FB VLDO1
l
0.76
0.8 0.2 0.2
0.84
V %/V % mA
ILDO1_STBY = 1mA, LDO1_STBY = 3.3V, VIN = 2.7V to 5.5V ILDO1 = 0.1mA to 25mA, LDO1_STBY = 3.3V
l
25 65 100 280 0.1 VIN 14 0 50 0.735 0.351 0.75 12.5 0.3625 0.373 19 1 80 0.765 180 -0.1
mA mV A V A A A V mV V
ILDO1 = 25mA, LDO1_STBY = 3.3V VLDO1_FB = 0.85V
l
LDO Regulator 2 (LDO2) 1.7 EN_LDO2 = High, LDO2_FB = 0.85V EN_LDO2 = Low EN_LDO2 = High L2DTV1 = L2DTV2 = 11111
l l l l
LDO2 Line Regulation LDO2 Load Regulation IOUT2 ISC2 VDROP2 ILDO2_FB VIN_LDO34 IVIN_LDO34 IVIN VLDO3 LDO2 Available Output Current LDO2 Short-Circuit Current Limit Dropout Voltage (Note 4) LDO2_FB Input Current VIN_LDO34 Input Range VIN_LDO34 Quiescent Current VIN_LDO34 Shutdown Current VIN Quiescent Current LDO3 Output Voltage LD03 Line Regulation LDO3 Load Regulation ILDO3 ILDO3_SC VDROP3 LDO3 Available Output Current LDO3 Short-Circuit Current Limit LDO3 Dropout Voltage (Note 4)
0.1 0.1 250 300 420 130 330 -0.1
l
%/V % mA 600 180 500 0.1 VIN mA mV mV A V A A A V %/V % mA 600 250 mA mV
ILDO2 = 200mA, VLDO2 = 2.5V ILDO2 = 200mA, VLDO2 = 1.2V VLDO2_FB = 0.8V
LDO Regulator 3 (LDO3) 2.35 14 0 50 1.746 1.8 0.1 0.1
l
EN_LDO3 = High, LDO3_FB = 0.85V Regulator Disabled VIN_LDO34 = VIN = 2.7V to 5V, ILDO3 = 1mA ILDO3 =1mA, VINLDO34 = 2.7V to 5.5V ILDO3 = 1mA to 250mA
l l l l
24 1 80 1.854
250 300 420 180
ILDO3 = 200mA, VLDO3 = 1.8V
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LTC3589 ELECTRICAL CHARACTERISTICS
SYMBOL VIN_LDO34 IVIN_LDO34 IVIN VLDO4 PARAMETER VIN_LDO34 Input Range VIN_LDO34 Quiescent Current VIN_LDO34 Shutdown Current Enabled VIN Quiescent Current LDO 4 Output Voltage ILDO4 = 1mA, L2DTV2[6:5] = 00 L2DTV2[6:5] = 01 L2DTV2[6:5] = 10 L2DTV2[6:5] = 11 ILDO4 =1mA, VINLDO4 = 2.7V to 5.5V, VOUT = 1.8V ILDO4 = 1mA to 250mA
l
The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_LDO2 = VIN_LDO34 = DVDD = 3.8V. All regulators disabled unless otherwise noted.
CONDITIONS
l
MIN 2.35
TYP
MAX VIN
UNITS V A A A V V V V %/V % mA
LDO Regulator 4 (LDO4) LDO4 Enabled, LDO4_FB = 0.85V LDO4 Disabled
l l l l l l l
14 0 50 2.716 2.245 1.746 3.201 2.8 2.5 1.8 3.3 0.1 0.1 250 300 420 100 180
22 1 80 2.884 2.575 1.854 3.399
LD04 Line Regulation LDO4 Load Regulation ILDO4 ILDO4_SC VDROP4 Enable Inputs VENx_THR VENx_THR2 VENx_THF2 RENX V VSTB_THR V VSTB_THF RVSTB VPWR_ONTHR VPWR_ONTHF RPWR_ON I2C Port DVDD IDVDD VDVDD_UVLO ADDRESS DVDD Input Supply Voltage DVDD Quiescent Current DVDD UVLO Level LTC3589 Device Address - Write LTC3589 Device Address - Read Threshold Rising, All Enables Low Threshold Rising, Any Enable High Threshold Falling, Any Enable High Input Pull-Down Resistance VSTB Pin Threshold Rising VSTB Pin Threshold Falling Pull-Down Resistence PWR_ON Pin Threshold Rising PWR_ON Pin Threshold Falling Pull-Down Resistence LDO4 Available Output Current LDO4 Short Circuit Current Limit LDO4 Dropout Voltage (Note 4)
600 130 250 1.2 0.525
mA mV mV V V V M
ILDO4 = 200mA, VLDO4 = 3.3V ILDO4 = 200mA, VLDO4 = 1.8V
l l l
0.8 0.425 0.5 0.45 4.5
VSTB, PWR_ON Inputs
l l l l
0.4
0.8 0.7 4.5 0.8 0.7 4.5
1.2
V V M V V M
1.2
0.4
1.6 SCL/SDA = 0kHz 0.3 1 01101000 01101001 70
5.5
V A V
VIH SDA, SCL SDA and SCL Input Threshold Rising VIL SDA, SCL SDA and SCL Input Threshold Falling IIHSCx IILSCx VOL SDA fSCL tBUF tHD_STA tSU_STA tSU_STO tHD_DAT(O) SDA and SCL Input Current SDA Output Low Voltage SCL Clock Operating Frequency Bus Free Time Between Stop and Start Condition Hold Time After (Repeated) Start Condition Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time Output SDA = SCL = 0V to 5.5V ISDA = 3mA
30 -1 1 0.4 400 1.3 0.6 0.6 0.6 0 900
%DVDD %DVDD A V kHz s s s s ns
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LTC3589 ELECTRICAL CHARACTERISTICS
SYMBOL tHD_DAT(I) tSU_DAT tLOW tHIGH tf tr tSP VON_TH I ON t ON_PBSTAT1 t ON_PBSTAT2 t ON_WAKE t ON_HR tPBSTAT_PW tPBSTAT_BK tWAKE_OFF tWAKE_ON tPWR_ON tPWR_OFF VPBSTAT IPBSTAT V WAKE IWAKE VPGOOD IPGOOD VPGOOD VNRSTO VUVLO VUVWARN VRSTO I RSTO VIRQ I IRQ PARAMETER Data Hold Time Input Data Setup Time SCL Clock Low Period SCL Clock High Period Clock/Data Fall Time Clock/Data Rise Time Input Spike Supression Pulse Width ON Threshold Rising ON Threshold Falling ON Input Current ON Low Time to PBSTAT Low ON High Time to PBSTAT High ON Low Time to WAKE High ON Low time to Hard Reset PBSTAT Minimum Pulse Width PBSTAT Blanking from WAKE Low Minimum WAKE Low Time WAKE High Time with PWR_ON = 0V PWR_ON High to WAKE High PWR_ON Low WAKE Low PBSTAT Output Low Voltage PBSTAT Output High Leakage Current WAKE Output Low Voltage WAKE Output High Leakage Current PGOOD Output Low Voltage PGOOD Output High Leakage Current PGOOD Threshold Rising PGOOD Threshold Falling LDO1 Power Good Threshold Rising LDO1 Power Good Threshold Falling Undervoltage Lockout Rising Undervoltage Lockout Falling Undervoltage Warning Rising Undervoltage Warning Falling RSTO Output Low Voltage RSTO Output High Leakage Current IRQ Output Low Voltage IRQ Output High Leakage Current I RSTO = 3mA VRSTO = 3.8V I IRQ = 3mA VIRQ = 3.8V -0.1 -0.1 IPBSTAT = 3mA VPBSTAT = 3.8V IWAKE = 3mA V WAKE = 3.8V IPGOOD = 3mA VPGOOD = 3.8V -0.1 -6 -8 -6 -8 2.65 2.55 3 2.9 0.4 0.1 0.4 0.1 V A V A
3589p
The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_LDO2 = VIN_LDO34 = DVDD = 3.8V. All regulators disabled unless otherwise noted.
CONDITIONS MIN 0 100 1.3 0.6 CB = Capacitance of One BUS Line (pF) CB = Capacitance of One BUS Line (pF) 20 + 0.1CB 20 + 0.1CB 300 300 50
l l
TYP
MAX
UNITS ns ns s s ns ns ns V V A A ms s ms s ms s s s ms ms
Pushbutton Interface 0.4 -1 40 50 0.2 400 5 50 1 1 5 50 50 0.1 -0.1 0.1 -0.1 0.1 0.4 0.1 0.4 0.1 0.4 0.1 0.8 0.7 1.2 1
ON = VIN ON = 0V
Status Output Pins (PBSTAT, WAKE, PGOOD, RSTO, IRQ) V A V A V A % % % % 2.7 V V
7
LTC3589 ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed Under Absolute Maximum ratings may cause permanent damage to the device. Exposure to any Absolute Maximum rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3589 is tested under pulsed load conditions such that TJ TA. The LTC3589E is guaranteed to meet specifications from 0C to 85C junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3589I is guaranteed over the -40C to 125C operating junction temperature range and the LTC3589H is guaranteed over the full -40C to 150C operating junction temperature range. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125C. The junction temperature (TJ in C) is calculated from the ambient temperature (TA in C) and power dissipation (PD, in Watts) according to the formula: TJ = TA + (PD * JA), where the package junction to ambient thermal impedance JA = 34C/W. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: The LTC3589 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 150C when overtemperature protection is active. Continuous operation above the specified maximum operating temperature may impair device reliability. Note 4: Dropout voltage is defined as (VIN - VLDO) for LDO1 or (VIN_LDO - VLDO) for other LDOs when VLDO is 3% lower than VLDO measured with VIN = VIN_LDO = 4.3V. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. Note 6: Soft-Start measured in test mode with regulator error amplifier in unity gain mode.
TYPICAL PERFORMANCE CHARACTERISTICS
Standby IVIN vs VIN
14 12 200 10 IVIN (A) IVIN (A) 8 6 4 50 2 0 2.5 0 2.5 ENABLE TWO LDOs 250 ALL REGULATORS DISABLED ENABLE THREE LDOs
TA = 25C, unless otherwise noted. Step-Down Switching Regulator IDD vs VIN
900 800 700 600 IVIN (A) ENABLE TWO BUCKS 500 400 300 200 100 ENABLE ONE BUCK ENABLE THREE BUCKS PULSE-SKIPPING MODE
LDO2 to LDO4 IDD IVIN vs VIN
150
100
ENABLE ONE LDO
3.0
3.5
4.5 4.0 VOLTAGE (V)
5.0
5.5
3.0
3.5
4.5 4.0 VOLTAGE (V)
5.0
5.5
3589 G02
0 2.5
3.0
3.5
4.5 4.0 VOLTAGE (V)
5.0
5.5
3589 G03
22554 G01
Step-Down Switching Regulator IDD vs VIN
120 100 80 IVIN (A) 60 40 20 0 2.5 Burst Mode OPERATION ENABLE THREE BUCKS 1200 1000 800 IVIN (A)
Input Supply Current vs Temperature
450 400 ALL REGULATORS ENABLED PULSE-SKIPPING MODE IVIN (A) 350 300 250 200 150 100 200 50 STANDBY (ONLY LDO1 ON) 0 -50 -25
Buck-Boost IDD vs VIN
ENABLE TWO BUCKS ENABLE ONE BUCK
FORCED CONTINUOUS
600 400 ALL REGULATORS ENABLED Burst Mode OPERATION
Burst Mode OPERATION
3.0
3.5
4.5 4.0 VOLTAGE (V)
5.0
5.5
3589 G04
0
25 50 75 100 125 TEMPERATURE (C)
150
0 2.5
3.0
3.5
4.0 4.5 VOLTAGE (V)
5.0
5.5
3589 G06
3589 G05
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LTC3589 TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency vs Temperature
2.30 2.25 FREQUENCY (MHz) 2.20 2.15 2.10 2.05 2.00 1.95 -50 PERCENT CHANGE (%) 1.0 0.8 0.6 EFFICIENCY (%) 0.4 0.2 0 -0.2 -0.4 -0.6 -10 110 70 TEMPERATURE (C) 30 150
3589 G07
TA = 25C, unless otherwise noted.
Switching Frequency Change vs VIN
100 90 80 70 60 50 40 30 20 10 3.0 3.5 4.5 4.0 VOLTAGE (V) 5.0 5.5
3589 G08
Buck-Boost Efficiency vs IOUT
VIN = 3.8V BURST
FORCED CONTINUOUS
VOUT = 5.0V VOUT = 2.5V VOUT = 3.3V 0.1 1 10 100 LOAD CURRENT (mA) 1000
3589 G9
-0.8 2.5
0 0.01
Buck-Boost Efficiency vs IOUT
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.01 0.1 VIN = 5.0V VIN = 4.2V VIN = 3.0V 1 10 100 LOAD CURRENT (mA) 1000
3589 G10
Step-Down Switching Regulator 1 Efficiency vs IOUT
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.01 0.1 PULSE-SKIPPING FORCED CONTINUOUS VOUT = 1.2V BURST EFFICIENCY (%) 100 90 80 70 60 50 40 30 20 10
Step-Down Switching Regulator 2 Efficiency vs IOUT
VOUT = 1.8V BURST
VOUT = 3.3V BURST
FORCED CONTINUOUS
FORCED CONTINUOUS
PULSE-SKIPPING 0.1 1 10 100 LOAD CURRENT (mA) 1000
3589 G12
1 10 100 LOAD CURRENT (mA)
1000
3589 G11
0 0.01
Step-Down Switching Regulator 3 Efficiency vs IOUT
100 90 80 EFFICIENCY (%) 70 RDS(ON) () 60 50 40 30 20 10 0 0.01 0.1 1 10 100 LOAD CURRENT (mA) 1000
3589 G13
Step-Down Switching Regulator RDS(ON) vs Temperature
0.40 0.35 0.25
Buck-Boost RDS(ON) vs Temperature
VOUT = 1.2V
BURST PULSESKIPPING
0.30 BUCK2 PMOS RDS(ON) () 0.25 0.20 BUCK2 NMOS 0.15 0.10 BUCK1 NMOS 0.05 0 -50 -10 110 70 TEMPERATURE (C) 30 150
3589 G14
0.20 PMOS BUCK1 PMOS 0.15 NMOS 0.10
FORCED CONTINUOUS
0.05
0 -50
-10
30 110 70 TEMPERATURE (C)
150
3589 G15
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9
LTC3589 TYPICAL PERFORMANCE CHARACTERISTICS
Step-Down Switching Regulator Current Limit vs Temperature
3.5 3.0 CURRENT LIMIT (A) 2.5 2.0 1.5 1.0 0.5 0 -50 -25 BUCK2, BUCK3 BUCK1 3.5 3.0 CURRENT LIMIT (A) 2.5 2.0 1.5 1.0 0.5 0 -50 -25 200s/DIV
3589 G18
TA = 25C, unless otherwise noted.
Buck-Boost Current Limit vs Temperature
PEAK LIMIT CLAMP LIMIT 500mV/DIV
Step-Down Switching Regulator Soft-Start
VOUT
200mA/DIV
IL
0
75 100 125 150 TEMPERATURE (C) 25 50
3589 G16
0
25 50 75 100 125 150 TEMPERATURE (C)
3589 G17
Buck-Boost Switching Regulator Soft-Start
VOUT 1V/DIV
Dynamic Voltage Slew
Step-Down Switching Regulator 1 Load Step
VOUT
VOUT PGOOD
50mV/DIV
500mA/DIV IL
VSTB 1A/DIV 100s/DIV
3589 G19
ILOAD
200s/DIV VRRCR = 1.75mV/s
3589 G20
40s/DIV PULSE-SKIPPING MODE
3589 G21
Step-Down Switching Regulator 1 Load Step
VOUT
Buck-Boost Switching Regulator 1 Load Step
2.5 VOUT LOAD CURRENT (A)
Maximum Buck-Boost Load Current vs VIN
VIN = 3.0V
50mV/DIV
200mV/DIV
2.0
1.5
ILOAD 1A/DIV 40s/DIV Burst Mode OPERATION
3589 G22
ILOAD
1.0 VOUT = 1.5V VOUT = 3.3V VOUT = 5V
1A/DIV
0.5 40s/DIV
3589 G23
0 2.5
3.0
3.5
4.5 4.0 VOLTAGE (V)
5.0
5.5
3589 G24
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LTC3589 TYPICAL PERFORMANCE CHARACTERISTICS
LDO1 Dropout Voltage vs Temperature
500 VLDO1 = 1.8V DROPOUT VOLTAGE (mV) 400 CHANGE IN VLDO1 (%) 0.0 0.5
TA = 25C, unless otherwise noted.
LDO1 Output Change vs VIN
80 VLDO1 = 25mA SHORT-CIRCUIT CURRENT (mA) 70 60 50 40 30
LDO1 Short-Circuit Current vs Temperature
300 VLDO1 = 3.3V 200
-0.5
-1.0 VLDO1 = 1.2V VLDO1 = 1.8V VLDO1 = 2.8V VLDO1 = 3.3V 2 3 4 VIN (V)
3589 G26
100
-1.5
0 -50 -25
-2.0 0 75 100 125 150 TEMPERATURE (C)
3589 G25
25
50
5
20 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
3589 G27
LDO2, LDO3, LDO4 Dropout Voltage vs Temperature
500 500
LDO2, LDO3, LDO4 Dropout Voltage vs Load Current
500 SHORT-CIRCUIT CURRENT (mA) 250
3589 G29
LDO2, LDO3, LDO4 Short-Circuit Current vs Temperature
DROPOUT VOLTAGE (mV)
DROPOUT VOLTAGE (mV)
400
VLDO = 1.2V
400 VLDO = 1.2V 300 VLDO = 1.8V 200
450 400 350 300 250 200 -50 -25
300 VLDO = 1.8V 200
100
VLDO = 3.3V
100 VLDO = 3.3V
0 -50 -25
0
75 100 125 150 TEMPERATURE (C)
3589 G28
25
50
0 0 50 150 200 LOAD CURRENT (mA) 100
0
25 50 75 100 125 150 TEMPERATURE (C)
3589 G30
LDO2, LDO3, LDO4 Enable Response
VLDO4 =2.8V VLDO3 =1.8V 1V/DIV VLDO2 =1.2V VLDO 50mV/DIV
LDO2, LDO3, LDO4 Load Step Response
LDO1 Load Step Response
1.8V
VLDO1 50mV/DIV
1.2V
220mA VEN_LDO2,VEN_LDO34 ILDO 100mA/DIV 10mA ILDO 10mA/DIV
20mA
1mA
100s/DIV
3589 G31
100s/DIV LOAD CAPACITANCE = 1F
3589 G32
40s/DIV
3589 G33
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LTC3589 PIN FUNCTIONS
VIN_LDO2 (Pin 1): Power Input for LDO2. This pin should be bypassed to ground with a 1F or greater ceramic capacitor. LDO2 (Pin 2): Output Voltage of LDO2. Nominal output voltage is set with a resistor feedback divider that servos to an I2C register controlled DAC reference. This pin must be bypassed to ground with a 1F or greater ceramic capacitor. LDO3 (Pin 3): Output Voltage of LDO3. Nominal output voltage is fixed at 1.8V. This pin must be bypassed to ground with a 1F or greater ceramic capacitor. LDO4 (Pin 4): Output Voltage of LDO4. Output voltages of 1.8V, 2.5V, 2.8V, and 3.3V are selected via the I2C port. This pin must be bypassed to ground with a 1F or greater ceramic capacitor. VIN_LDO34 (Pin 5): Power Input for LDO3 and LDO4. This pin should be bypassed to ground with a 1F or greater ceramic capacitor. PVIN1 (Pin 6): Power Input for Step-Down Switching Regulator 1. This pin should be bypassed to ground with a 4.7F or greater ceramic capacitor. SW1 (Pin 7): Switch Pin for Step-Down Switching Regulator 1. Connect one side of step-down switching regulator 1 inductor to this pin. RSTO (Pin 8): Reset Output. Open drain output pulls low when the always on regulator LDO1 is below regulation and during a hard reset initiated by a pushbutton input. EN_LDO2 (Pin 9): Enable LDO2 Logic Input. Active high input to enable LDO2. A weak pull-down forces EN_LDO2 low when left floating. EN1 (Pin 10): Enable Step-Down Switching Regulator 1. Active high input to enable step-down switching regulator 1. A weak pull-down forces EN1 low when left floating. EN2 (Pin 11): Enable Step-Down Switching Regulator 2. Active high input to enable step-down switching regulator 2. A weak pull-down forces EN2 low when left floating. SW4AB (Pin 12): Switch Pin for Buck-Boost Switching Regulator 4. Connected to the buck-boost internal power switches A and B. Connect an inductor between this pin and SW4CD (Pin 19). EN3 (Pin 13): Enable Step-Down Switching Regulator 3. Active high input to enable step down switching regulator 3. A weak pull-down forces EN3 low when left floating. EN4 (Pin 14): Enable Buck-Boost Switching Regulator 4. Active high input to enable buck-boost switching regulator 4. A weak pull-down forces EN4 low when left floating. PVIN4 (Pin 15): Power Input for Switching Regulator 4. This pin should be bypassed to ground with a 4.7F or greater ceramic capacitor. BB_OUT (Pin 16): Output Voltage of Buck-Boost Switching Regulator 4. This pin must be bypassed to ground with a 22F or greater ceramic capacitor. IRQ (Pin 17): Interrupt Request Output. Open drain driver is pulled low for power good, undervoltage, and over temperature warning and fault conditions. Clear IRQ by writing to the I2C CLIRQ command register. EN_LDO34 (Pin 18): Enable LDO3 and LDO4 Logic Input. Active high to enable LDO3 and LDO4. Disable LDO4 via I2C software commands using I2C command registers OVEN or L2DTV2. A weak pull-down forces EN_LDO34 low when left floating. SW4CD (Pin 19): Switch Pin for Buck-Boost Switching Regulator 4. Connected to the buck-boost internal power switches C and D. Connect an inductor between this node and SW4AB (Pin 12). PWR_ON (Pin 20): External Power-On. Handshaking pin to acknowledge successful power-on sequence. PWR_ON must be driven high within five seconds of WAKE going high to keep power on. It can be used to activate the WAKE output by driving high. Drive low to shut down WAKE. ON (Pin 21): Pushbutton Input. A weak internal pull-up forces ON high when left floating. A normally open pushbutton is connected from ON to ground to force a low state on this pin.
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LTC3589 PIN FUNCTIONS
PBSTAT (Pin 22): Pushbutton Status. Open drain output to be used for processor interrupts. PBSTAT mirrors the status of ON pushbutton pin. PBSTAT is delayed 50ms from ON pin for debounce. WAKE (Pin 23): System Wake Up. Open drain driver output releases high when signaled by pushbutton activation or PWR_ON input. It may be used to initiate a pin-strapped power-up sequence by connecting to a regulator enable pin to initiate a pin strapped power-on sequence. PVIN2 (Pin 24): Power Input for Step-Down Switching Regulator 2. This pin should be bypassed to ground with a 4.7F or greater ceramic capacitor. SW2 (Pin 25): Switch Pin for Step-Down Switching Regulator 2. Connect one side of step-down switching regulator 2 inductor to this pin. SW3 (Pin 26): Switch Pin for Step-Down Switching Regulator 3. Connect one side of step-down switching regulator 3 inductor to this pin. PVIN3 (Pin 27): Power Input for Switching Regulator 3. Tie this pin to the VIN supply. This pin should be bypassed to ground with a 4.7F or greater ceramic capacitor. VSTB (Pin 28): Voltage Standby. When VSTB is low, DAC reference voltages are selected by bit values in command register VCCR. When VSTB is high, the DAC voltages are forced to the bit values found in the V2 registers. Tie VSTB to ground if unused. PGOOD (Pin 29): Power Good Output. Open drain output pulls down when any regulator falls below power good threshold and during regulator dynamic voltage slew. Unless disabled in I2C register. Pulls down when all regulators are disabled. SCL (Pin 30): Clock Input Pin for the I2C Serial Port. The I2C logic levels are scaled with respect to DVDD. SDA (Pin 31): Data Input Pin for the I2C Serial Port. The I2C logic levels are scaled with respect to DVDD. DVDD (Pin 32): Supply Voltage for I2C Serial Port. This pin sets the logic reference level of SCL and SDA I2C pins. DVDD resets I2C registers to power on state when driven to <1V. SCL and SDA logic levels are scaled to DVDD. Connect a 0.1F decoupling capacitor from this pin to ground. BUCK2_FB (Pin 33): Feedback Input for Step-Down Switching Regulator 2. Set full scale output voltage using resistor divider connected from the output of step-down switching regulator 2 to this pin to ground. BUCK3_FB (Pin 34): Feedback Input for Step-Down Switching Regulator 3. Set full scale output voltage using resistor divider connected from the output of step-down switching regulator 3 to this pin to ground. LDO1_FB (Pin 35): Feedback Input for LDO1. Set output voltage using a resistor divider connected from LDO1_STDBY to this pin to ground. LDO1_STDBY (Pin 36): Always On LDO1 Output. This pin provides an always on supply voltage useful for light loads such as a watchdog microprocessor or a real time clock. Connect a 1F capacitor from LDO1_STBY to ground. VIN (Pin 37): Supply Voltage Input. This pin should be bypassed to ground with a 1F or greater ceramic capacitor. LDO2_FB (Pin 38): Feedback Input for LDO2. Set full scale output voltage using a resistor divider connected from LDO2_OUT to this pin to ground. BUCK1_FB (Pin 39): Feedback Input for Step-Down Switching Regulator 1. Set full scale output voltage using resistor divider connected from the output of step-down switching regulator 1 to this pin to ground. BB_FB (Pin 40): Feedback Input for Buck-Boost Switching Regulator 4. Set the output voltage using resistor divider connected from BB_OUT to this pin to ground. GND (Exposed Pad Pin 41): Ground. The Exposed Pad must be connected to a continuous ground plane on the second layer of the printed circuit board by several interconnect vias directly under the LTC3589 for maximum heat transfer.
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LTC3589 BLOCK DIAGRAM
VIN VREF VRTC AT 25mA BUCK-BOOST SW4AB PVIN4 BB_OUT I/O AT 1.2A
LDO1_STDBY OK LDO1_FB ALWAYS ON LDO1
VREF
SW4CD
EN OK IRQ ON (PB) PBSTAT WAKE PWR_ON VSTB DAC CONTROL + SEQUENCE EN OK VREF SW1 VCORE AT 1.6A BUCK 1 BB_FB PVIN1
EN1 EN-PINS EN2 EN3 EN4 EN_LDO2 EN_LDO34 DAC n EN OK VREF EN-I2C BUCK 2
BUCK1_FB PVIN2
SW2
VSRAM AT 1A
BUCK2_FB DVDD PVIN3 SDA SCL PGOOD I2C BUCK 3 VSOC AT 1A
EN OK DAC VREF 7
SW3
RSTO
BUCK3_FB POWER GOOD VREF LDO2 VMEM AT 250mA VIN_LDO2
DAC
EN OK VIN_LDO34 LDO4 LDO3 VREF EN OK
LDO2 LDO2_FB
VREF EN OK
0V, 1.8V, 2.5V, 2.8V, 3.3V AT 250mA
LDO4
LDO3
VANALOG 1.8V AT 250mA
GND (EXPOSED PAD)
3589 BD
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LTC3589 OPERATION
INTRODUCTION The LTC3589 is a complete power management solution for portable microprocessors and peripheral devices. It generates a total of eight voltage rails for supplying power to the processor core, SDRAM, system memory, PC cards, always-on real time clock and HDD functions. Supplying the voltage rails are an always-on low quiescent current 25mA LDO, one 1.6A and two 1A step-down regulators, a 1.2A buck-boost regulator, and three 250mA low dropout regulators. Supporting the multiple regulators is a highly configurable power-on sequencing capability, dynamic voltage slewing DAC output voltage control, a pushbutton interface controller, regulator control via an I2C interface, and extensive status and interrupt outputs. The LTC3589 operates over an input supply range of 2.7V to 5.5V. The input supplies for the 250mA LDO regulators may operate as low as 1.7V to limit power loss at low output voltages. The always-on LDO1 provides a resistor programmable output voltage as low as 0.8V and is capable of supplying 25mA. With only the always-on LDO active the LTC3589 draws just 10A (typical). Always on LDO1 will continue to operate with VIN levels as low as 2.0V (typical) to maintain memory and RTC function as long as possible. Each of the 250mA LDO regulators has unique output voltage configurations. LDO3 has a fixed 1.8V output. LDO4 has four output levels selectable via the I2C interface. Its possible outputs are 1.8V, 2.5V, 2.8V, and 3.3V. LDO2 has a dynamically slewing DAC set point reference and an external feedback pin to set the output voltage range with a resistive divider. Each LDO draws 60A (typical) quiescent current. The LTC3589 includes three internally compensated constant frequency current mode step-down switching regulators providing 1A, 1A, and 1.6A. Step-down regulator switching frequencies of 2.25MHz or 1.125MHz are independently selected for each step-down regulator using the I2C command registers. The power-on default frequency is 2.25MHz. Each of the step-down regulators have dynamically slewing DAC input references and external feedback pins to set output voltage range. The step-down regulators three operating modes, pulse-skipping, burst, or forced continuous, are set using the I2C interface. In pulse-skipping mode the regulator will support 100% duty cycle. For best efficiency at low output loads select Burst Mode operation. Forced continuous mode minimizes output voltage ripple at light loads. The 4-switch buck-boost DC/DC voltage mode converter generates a user-programmable output voltage rail from 2.5V to 5V. Utilizing a proprietary switching algorithm, the buck-boost converter maintains high efficiency and low noise operation with input voltages that are above, below or equal to the required output rail. The buck-boost error amplifier uses a fixed 0.8V reference and the output voltage is set by an external resistor divider. Burst Mode operation is enabled through the I2C control registers. No external compensation components are required for the buck-boost converter. The reference inputs for the three step-down regulators and LDO2 are 5-bit D to A converters with up-down ramping at selectable slew rates. The slew endpoint voltages and select bits are stored in I2C registers for each DAC. A select bit in the I2C command registers chooses which register to use for each target voltage. Variable reference slew rates from 0.88mV/s to 7mV/s are selectable in the I2C register. Each of the four DACs has independent voltage, voltage select, and slew rate control registers. The LTC3589 is equipped with a pushbutton control circuit that will activate the WAKE output, indicate pushbutton status via the PBSTAT pin, and initiate a hard reset shutdown of the regulators. Grounding the ON pin with the pushbutton for 400ms will force the WAKE pin to release HIGH. The WAKE pin output can be tied to the enable pin of the first regulator in a power-on sequence. Once in the power-on state, subsequent pushes of the button longer than 50ms are mirrored by the PBSTAT output. Holding ON LOW for five seconds disables all the regulators, pulls down the WAKE pin, and pulls down RSTO for one second to indicate to the processor that a hard reset occurred. All regulator enables and pushbutton inputs are inhibited for one second following the hard reset. The LTC3589 has flexible options for enabling and sequencing the regulator enables. The regulators are enabled using input pins or the I2C serial port. To define a power-on
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LTC3589 OPERATION
sequence tie the enable of the first regulator to be powered up to the WAKE pin. Connect the first regulators output to the enable pin of the second regulator, and so on. One or more regulators may be started in any sequence. Each enable pin has a 200s (typical) delay between the pin and the internal enable of the regulator. When the system controllers are satisfied that power rails are up, the controller must drive PWR_ON HIGH to keep WAKE active. Shutdown sequencing is monitored by output voltage comparators which require each output to discharge below 300mV before re-enabling. A software control command register function is available which sets the regulators to effectively ignore their enable pins but respond to I2C register enables. This function enables software-only control of any combination of pin-strapped regulators and is useful for implementing system power saving modes. Keep-alive mode exempts selected regulators from turning off during normal shutdown. In keep-alive mode, the LTC3589 powers down normally and is ready for the next start-up sequence, but selected regulators are kept on to power memory or other function during system standby modes. The LTC3589 will shut down all regulators and pull down the WAKE pin under high temperature, VIN under voltage, and extended low regulator output voltage conditions. Status of a hard shutdown is reported by the IRQ status pin and the IRQSTAT status register. The I2C serial port on the LTC3589 contains 13 command registers for controlling each of the regulators, one read only register for monitoring each regulators power good status, one read only register for reading the cause of an IRQ event, and one clear IRQ command register. The LTC3589 I2C supports random addressing of any register and registers may be written in any order using multiple START sequences. ALWAYS-ON LDO The LTC3589 includes a low quiescent current low dropout regulator that remains powered whenever a valid supply is present on VIN. The always-on LDO will remain active until VIN drops below 2.0V (typical). This is below the 2.5V undervoltage threshold in effect for the rest of the LTC3589 circuits. The always-on LDO is used to provide power to a standby microcontroller, real time clock, or other keep-alive circuits. The LDO is guaranteed to support a 25mA load. A 1F low impedance ceramic bypass capacitor from LDO1_STBY to GND is required for compensation. A power good monitor pulls RSTO LOW for a minimum of 14ms (typical) whenever LDO1_STBY is 8% below its regulation target. An LDO1_STBY undervoltage condition is reported in the PGOOD status register. The output voltage of LDO1 is set with a resistor divider connected from LDO1_STBY to the feedback pin LDO1_FB as shown in Figure 1. VLDO_STBY = 0.8 * 1+ R1 (V) R2
Typical values for R1 are in the range of 40k to 1M.
+ - LDO1_STBY R1 LDO1_FB
3589 F01
VIN
0.8V
1F
R2
Figure 1. Always-On LDO Application Circuit
LDO1_STBY is protected from short circuits and over loading. 250MA LDO REGULATORS Three LDO regulators on the LTC3589 will each deliver up to 250mA output. The LDO regulators are enabled by pin input or I2C command register. Pin EN_LDO2 enables LDO2 and pin EN_LDO34 enables LDO3 and LDO4 together. An I2C command register bit is available to decouple LDO4 from pin EN_LDO34 so that LDO4 is under command register control only. All the regulators have current limit protection circuits. When disabled, a 2k internal pull-down resistor is connected to the regulators output. Depending on settings in I2C system control register 2 (SCR2), a regulator's output must discharge to less than 300mV before it will respond to its enable. The output discharge
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LTC3589 OPERATION
feature is to guarantee proper startup sequencing. This feature and the 2k pull-down resistors may be overridden by bit settings in command register SCR2. To help reduce LDO power loss in the system, the regulators have dedicated supply inputs that may be lower than the main VIN supply. Connect a low ESR 1F capacitor to each of the output pins LDO2, LDO3, and LDO4. LDO Regulator 2 One of the LTC3589 dynamic slewing DACs serves as the reference input of LDO2. The output range of LDO2 is set using an external resistor divider connected from LDO2 to the feedback pin LDO2_FB as shown in Figure 2. Set the output voltage of LDO2 using the following formula: VOUT R1 * (0.3625 + L2DTVx * 0.0125) = 1+ R2 Table 1. Shows the I2C command register settings used to control LDO2.
Table 1. LDO 2 Command Register Settings
COMMAND REGISTER[BIT] OVEN[4] SCR2[4] VCCR[5] VCCR[6] VRRCR[7-6] VALUE 0* 1 0* 1 0* 1 1 00* 01 10 11 11001* 0* 1 0* 1 11001* SETTING Disable Enable Wait for Output Below 300mV Before Enable Enable Immediately Select Register L2DTV1 (V1) Reference Select Register L2DTV2 (V2) Reference Initiate Dynamic Voltage Slew Reference Slew Rate = 0.88mV/s Reference Slew Rate = 1.75mV/s Reference Slew Rate = 3.5mV/s Reference Slew Rate = 7mV/s DAC Dynamic Target Voltage V1 Force PGOOD Low When Slewing Normal PGOOD Operation When Slewing Shutdown LDO2 Normally Keep LDO2 Alive DAC Dynamic Target Voltage V2
L2DTV1[4-0] L2DTV1[5] L2DTV1[7] L2DTV2[4-0]
L2DTVx is the five bit word contained in the LDO2 dynamic target voltage 1 (L2DTV1) or the LDO2 dynamic target voltage 2 (L2DTV2) command registers. The default value of L2DTVx[4-0] is 11001 to output a reference voltage of 0.675V. LDO2 is enabled by writing bit 4 in the output voltage enable (OVEN) command register to 1 or driving the LDO2_EN pin high. Whenever the command is given to slew LDO2 DAC reference to a lower voltage an integrated 2k pull down resistor is connected to LDO2 output.
PVIN EA LDO2 0.3625V TO 0.75V FB R2 R1 1F
* Denotes Default Power-On Value
LDO Regulator 3 LDO3 is a fixed 1.8V output regulator. LDO3 is enabled by driving pin EN_LDO34 high or by writing command register OVEN[5] to 1. Table 2 shows the I2C command register settings used to control LDO3.
Table 2. LDO 3 Command Register Settings
COMMAND REGISTER[BIT] OVEN[5] SCR2[5] VALUE 0* 1 0* 1 SETTING Disable Enable Wait for Output Below 300mV Before Enable Enable Immediately
DAC
5
* Denotes Default Power-On Value
3589 F02
Figure 2. LDO2 Application Circuit
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LTC3589 OPERATION
LDO Regulator 4 LDO4 has four output voltage options that are controlled by the contents of command register L2DTV2 bits 6 and 5. By default, pin EN_LDO34 enables and disables LDO3 and LDO4 simultaneously when command register bits OVEN[6] and OVEN[7] are LOW. When EN_LDO34 is LOW, LDO3 and LDO4 are controlled by writing to command register bits OVEN[6] and OVEN[7] respectively. When command register bit L2DTV2[7] is HIGH, control of LDO4 is disconnected from pin EN_LDO34 and controlled by command register bit OVEN[7] regardless of the status of EN_LDO34. Table 3 shows the I2C command register settings used to control LDO4.
Table 3. LDO 4 Command Register Settings
COMMAND REGISTER[BIT] OVEN[6] SCR2[6] L2DTV2[6-5] VALUE 0* 1 0* 1 00* 01 10 11 0 1 SETTING Disable Enable Wait for Output Below 300mV Before Enable Enable Immediately VLDO4 = 2.8V VLDO4 = 2.5V VLDO4 = 1.8V VLDO4 = 3.3V LDO4 Enable Controlled by EN_LDO34 LDO4 Enable Controlled by OVEN[6]
EN MODE COUT CFB FB R2 0.3625V TO 0.75V 5 DAC R1 PWM CONTROL PVIN SW L1
3589 F03
Figure 3. Step-Down Switching Regulator Application Circuit
of 0.675V. Typical values for R1 are in the range of 40k to 1M. The capacitor CFB cancels the pole created by the feedback resistors and the input capacitance on the FB pin and also helps to improve load step transient response. A value of 10pF is recommended for most applications. Experimentation with capacitor sizes between 10pF and 33pF may yield improved transient response. Operating Modes The step-down switching regulators include three possible operating modes to meet the noise and power needs of a variety of applications. In pulse-skipping mode, at the start of every cycle, a latch is set that turns on the main P-channel MOSFET switch. During the cycle, a current comparator compares the peak inductor current to the output of an error amplifier. The output of the current comparator resets the latch. At this time the P-channel MOSFET switch turns off and the N-channel MOSFET synchronous rectifier turns on. The N-channel MOSFET synchronous rectifier will turn off when the end of the clock cycle is reached or if the inductor current drops through zero. Using this method of operation, the error amplifier adjusts the peak inductor current to deliver the required output power. All necessary loop compensation is internal to the step-down switching regulator requiring only a single ceramic output capacitor for stability. At light loads in pulse-skipping mode, the inductor current may reach zero on each pulse that will
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L2DTV2[7]
* Denotes Default Power-On Value
STEP-DOWN SWITCHING REGULATORS Output Voltage Programming Each of the step-down converters uses a dynamically slewing DAC output for its reference. The full-scale output voltage is set by using a resistor divider connected from the step-down switching regulator output to the feedback pins (B1_FB, B2_FB, and B3_FB) as shown in Figure 3. Set the output voltage of step-down switching regulators using the following formula: VOUT = 1+ R1 * (0.3625 + BxDTVx * 0.0125)(V) R2
BxDTVx is the decimal value of the five bit binary number in the I2C BxDTV1 or BxDTV2 command registers. BxDTV1 and BxDTV2 default to 11001 to output a reference voltage
18
LTC3589 OPERATION
turn off the N-channel MOSFET synchronous rectifier. In this case the switch node (SW1, SW2, or SW3) goes HIGH impedance and the switch node will ring. This is discontinuous operation and is normal behavior for a switching regulator. At very light loads in pulse-skipping mode, the step down switching regulators will automatically skip pulses as needed to maintain output regulation. At high duty cycle (VOUTX > VIN/2) it is possible for the inductor current to reverse at light loads causing the stepped down switching regulator to operate continuously. When operating continuously, regulation and low noise output voltage are maintained, but input operating current will increase to a few milliamps. In the forced continuous mode of operation, the inductor current is allowed to be less than zero over the full range of duty cycles. Operating in forced continuous mode is a lower noise option at light loads than pulse-skipping operation but with the drawback of higher VIN current due to the continuous operation of the MOSFET switch and rectifier. Since the inductor current is allowed to be negative in forced continuous operation the step-down switching regulator has the ability to sink output current. The LTC3589 automatically forces the step-down switching regulator into forced continuous mode when dynamically slewing the DAC voltage reference down. When the LTC3589 step-down switching regulators are in Burst Mode operation, they automatically switch between fixed frequency pulse-skipping operation and hysteretic Burst Mode control as a function of the load current. At light loads the step-down switching regulators control the inductor current directly and use a hysteretic control loop to minimize both noise and switching losses. While operating in Burst Mode operation, the output capacitor is charged to a voltage slightly higher than the regulation point. The step-down switching regulator then goes into a low power sleep mode during which the output capacitor provides the load current. In sleep mode most of the switching regulator's circuitry is powered off to conserve battery power. When the output voltage drops below the regulation point the regulator's circuitry is powered on and another burst cycle begins. As the load current increases, the time between burst cycles decreases. Above a load current about 1/4 rated output load, the step-down switching regulators will switch to low noise constant frequency PWM operation. Set the mode of operation for the step-down switching regulators by using the I2C command register SCR1. Each of the three regulators has independent mode control. A step-down switching regulator may enter a dropout condition when its input voltage drops to near its programmed output voltage. For example, a discharging battery voltage of 3.4V dropping to the regulators programmed output voltage of 3.3V. When this happens the duty cycle of the P-channel MOSFET switch is increased until it turns on continuously with 100% duty cycle. In dropout, the regulators output voltage equals the regulators input voltage minus the voltage drops across the internal P-channel MOSFET and the inductor DC resistance. Register Controls Table 4, Table 5, and Table 6 show the I2C command register settings used to control the step-down switching regulators.
Table 4. Step-Down Switching Regulator 1 Command Register Settings
COMMAND REGISTER[BIT] SCR1[1-0] VALUE 00* 01 10 0* 1 0* 1 0* 1 1 00* 01 10 11 0* 1 11001* 11001* 0 1 0* 1 0* 1 SETTING Pulse-Skipping Mode Burst Mode Operation Forced Continuous Mode Disable Enable Wait for Output Below 300mV Before Enable Enable Immediately Select Register B1DTV1 (V1) Reference Select Register B1DTV2 (V2) Reference Initiate Dynamic Voltage Slew Reference Slew Rate = 0.88mV/s Reference Slew Rate = 1.75mV/s Reference Slew Rate = 3.5mV/s Reference Slew Rate = 7mV/s Force PGOOD Low When Slewing Normal PGOOD Operation When Slewing DAC Dynamic Target Voltage V1 DAC Dynamic Target Voltage V2 2.25MHz Switching Frequency 1.125MHz Switching Frequency Switch on Clock Phase 1 Switch on Clock Phase 2 Shutdown Regulator 1 Normally Keep Regulator 1 Alive
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OVEN[0] SCR2[0] VCCR[1] VCCR[0] VRRCR[1-0]
B1DTV1[5] B1DTV1[4-0] B1DTV2[4-0] B1DTV2[5] B1DTV2[6] B1DTV2[7]
* Denotes Default Power-On Value
19
LTC3589 OPERATION
Soft-Start Soft-start is accomplished by gradually increasing the input reference voltage on each step-down switching regulator from 0V to the dynamic reference DAC output level at a rate of 2mV/s. This allows each output to rise slowly, helping minimize inrush current required to charge up the regulator output capacitor. A soft-start cycle occurs whenever a regulator is enabled either initially or while powering up following a fault condition. A soft-start cycle is not triggered by a change of operating modes or a dynamic voltage slew. During soft-start the converter is forced to pulse-skipping mode regardless of the settings in the SCR1 command register.
Table 5. Step-Down Switching Regulator 2 Command Register Settings
COMMAND REGISTER[BIT] SCR1[3-2] VALUE 00* 01 10 0* 1 0* 1 0* 1 1 00* 01 10 11 0* 1 11001* 11001* 0 1 0* 1 0* 1 SETTING Pulse-Skipping Mode Burst Mode Operation Forced Continuous Mode Disable Enable Wait for Output Below 300mV Before Enable Enable immediately Select Register B2DTV1 (V1) Reference Select Register B2DTV2 (V2) Reference Initiate Dynamic Voltage Slew Reference Slew Rate = 0.88mV/s Reference Slew Rate = 1.75mV/s Reference Slew Rate = 3.5mV/s Reference Slew Rate = 7mV/s Force PGOOD Low When Slewing Normal PGOOD Operation When Slewing DAC Dynamic Target Voltage V1 DAC Dynamic Target Voltage V2 2.25MHz Switching Frequency 1.125MHz Switching Frequency Switch on Clock Phase 1 Switch on Clock Phase 2 Shutdown Regulator 2 Normally Keep Regulator 2 Alive
Switching EMI Control The step-down switching regulators contain new patent pending circuitry to limit the edge rate of the switch nodes SW1, SW2, and SW3. This new circuitry controls the transition of the switch node over a period of a few nanoseconds, significantly reducing radiated EMI and conducted supply noise while maintaining high efficiency. Since slowing the slew rate of the switch nodes causes efficiency loss, the slew rate of the step-down switching regulators is adjustable using the I2C command register B1DTV1 bits 6 and 7. Optimize efficiency or EMI as necessary with four different slew rate settings. The power-on default is the fastest slew rate, highest efficiency setting.
Table 6. Step-Down Switching Regulator 3 Command Register Settings
COMMAND REGISTER[BIT] SCR1[5-4] VALUE 00* 01 10 0* 1 0* 1 0* 1 1 00* 01 10 11 0* 1 11001* 11001* 0 1 0* 1 0* 1 SETTING Pulse-Skipping Mode Burst Mode Operation Forced Continuous Mode Disable Enable Wait for Output Below 300mV Before Enable Enable Immediately Select Register B3DTV1 (V1) Reference Select Register B3DTV2 (V2) Reference Initiate Dynamic Voltage Slew Reference Slew Rate = 0.88mV/s Reference Slew Rate = 1.75mV/s Reference Slew Rate = 3.5mV/s Reference Slew Rate = 7mV/s Force PGOOD Low When Slewing Normal PGOOD Operation When Slewing DAC Dynamic Target Voltage V1 DAC Dynamic Target Voltage V2 2.25MHz Switching Frequency 1.125MHz Switching Frequency Switch on Clock Phase 1 Switch on Clock Phase 2 Shutdown Regulator 3 Normally Keep Regulator 3 Alive
OVEN[1] SCR2[1] VCCR[3] VCCR[2] VRRCR[3-2]
OVEN[2] SCR2[2] VCCR[5] VCCR[4] VRRCR[5-4]
B2DTV1[5] B2DTV1[4-0] B2DTV2[4-0] B2DTV2[5] B2DTV2[6] B2DTV2[7]
B3DTV1[5] B3DTV1[4-0] B3DTV2[4-0] B3DTV3[5] B3DTV2[6] B3DTV2[7]
* Denotes Default Power-On Value
* Denotes Default Power-On Value
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20
LTC3589 OPERATION
Operating Frequency The switching frequency of each of the LTC3589 stepdown switching regulators may be independently set using I2C command register bits B1DTV2[5], B2DTV2[5] and B3DTV2[5]. The power-on default frequency is 2.25MHz. Writing bit BxDTV2[5] HIGH will reduce the switching frequency to 1.125MHz. Selection of the operating frequency is determined by desired efficiency, component size and converter duty cycle. Operation at lower frequency improves efficiency by reducing internal gate charge and switching losses but requires larger inductance and capacitance values for comparable output ripple voltage. The lowest duty cycle of the step-down switching regulator is determined by the converters minimum on-time. Minimum on-time is the shortest time duration that the converter is capable of turning its top PMOS on and off again. The time consists of the gate charge time plus internal delays associated with peak current sensing. The minimum on-time of the LTC3589 is approximately 90ns. If the duty cycle falls below what can be accommodated by the minimum ontime, the converter will begin to skip cycles. The output voltage will continue to be regulated but the ripple voltage and current will increase. With the switching frequency set to 2.25MHz, the minimum supported duty cycle is 20%. Switching at 1.125MHz the converter can support a 10% duty cycle. Phase Selection To reduce the cycle by cycle peak current drawn by the switching regulators, the clock phase of each of the LTC3589 step-down switching regulators can be set using I2C command register bits B1DTV2[6], B2DTV2[6] and B3DTV2[6]. The internal full rate clock has a nominal duty cycle of 20% while the half rate clocks have a 50% duty cycle. Setting the command register bits high will delay the start of each converter switching cycle by 20% or 50% depending on the selected operating frequency. Inductor Selection The choice of step-down switching regulator inductor influences the efficiency of the converter and the magnitude of the output voltage ripple. Larger inductance values reduce inductor current ripple and therefore lower output voltage ripple. A larger value inductor improves efficiency by lowering the peak current to be closer to the average output current. Larger inductors, however, generally have higher series resistance that counters the efficiency advantage of reduced peak current. Inductor ripple current is a function of switching frequency, inductance, VIN, and VOUT as shown in this equation: IL = V 1 * VOUT 1- OUT VIN f *L
In an example application the LTC3589 step-down switching regulator 3 has a maximum load of 1A, VIN equals 3.8V, and VOUT is set for 1.2V. A good starting design point for inductor ripple is 30% of output current or 300mA. Using the equation for ripple current, a 1.2H inductor should be selected. An inductor with low DC resistance will improve converter efficiency. Select an inductor with a DC current rating at least 1.5 times larger than the maximum load current to ensure the inductor does not saturate during normal operations. If short circuit is a possible condition, the inductor should be rated to handle the maximum peak current specified for the step-down converter. Table 7 shows inductors that work well with the step-down switching regulators. Input/Output Capacitor Selection Low ESR (equivalent series resistance) ceramic capacitors should be used at both the output and input supply of the switching regulators. Only X5R or X7R ceramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. A 22F capacitor is sufficient for the step-down
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LTC3589 OPERATION
switching regulator outputs. For good transient response and stability the output capacitor should retain at least 10F of capacitance over operating temperature and bias voltage. Place at least 4.7F decoupling capacitance as close as possible to each PVIN pin. Refer to Table 11 for recommended ceramic capacitor manufacturers. BUCK-BOOST SWITCHING REGULATOR
EN PVIN4 A SW4AB B BB_OUT D SW4CD C
Output Voltage Programming Set the output voltage of the LTC3589 buck-boost switching regulator using an external resistor divider connected from BB_OUT to the feedback pin BB_FB and to GND as shown in Figure 4. VBB_OUT = 0.8 * 1+ R1 (V) R2
MODE
PWM CONTROL
R1 BB_FB 0.8V
3589 F04
22F
Figure 4. Buck-Boost Switching Regulator Application Circuit
Table 7. Inductors for Step-Down Switching Regulator 1
MANUFACTURERS Coilcraft PART NUMBER XPL4020-102ML XPL4020-152ML XPL4020-222ML LPS6225-222ML LPS6225-332ML LPS6225-472ML SD14-1R2-R SD14-1R5-R SD14-2R0-R SD25-2R2-R CDRH5D16NP-3R3N VLF5014ST-1R0N2R7 VLF5014st-2R2N2R3 VLCF5020T-2R2N2R6-1 1124BS-1R2N 1124BS-1R8N H-DI-0520-2R2 H-DI-0630-2R4 H-DI-0630-3R8 744042001 744052002 744053003 7440530047 7440430022 VALUE (H) 1.0 1.5 2.2 2.2 3.3 4.7 1.2 1.5 2.0 2.2 3.3 1.0 2.2 2.2 1.2 1.8 2.2 2.4 3.8 1.0 2.5 3.0 4.7 2.2 DCR () 0.029 0.036 0.060 0.045 0.055 0.065 0.034 0.039 0.045 0.031 0.045 0.050 0.073 0.071 0.047 0.056 0.048 0.028 0.040 0.028 0.030 0.024 0.030 0.023 MAX DC CURRENT (A) 4.00 3.60 2.60 3.90 3.50 3.00 3.35 2.91 2.56 2.80 2.60 2.7 2.3 2.6 2.9 2.7 2.6 2.5 2 2.60 2.4 2.8 2.4 2.5 SIZE (mm) W x L x H 4.2 x 4.2 x 2.0 4.2 x 4.2 x 2.0 4.2 x 4.2 x 2.0 6.0 x 6.0 x 2.0 6.0 x 6.0 x 2.0 6.0 x 6.0 x 2.0 5.2 x 5.2 x 1.45 5.2 x 5.2 x 1.45 5.2 x 5.2 x 1.45 5.2 x 5.2 x 2.5 5.6 x 5.6 x 1.8 4.8 x 4.6 x 1.4 4.8 x 4.6 x 1.4 5.0 x 5.0 x 2.0 4.5 x 4.7 x 1.8 4.5 x 4.7 x 1.8 5.3 x 5.3 x 2.0 6.3 x 6.3 x 3.0 6.3 x 6.3 x 3.0 4.8 x 4.8 x 1.8 5.8 x 5.8 x 1.8 5.8 x 5.8 x 2.8 5.8 x 5.8 x 2.8 4.8 x 4.8 x 2.8
Cooper
Sumida TDK
TOKO Tokin
Wurth
22
- +
R2
3589p
LTC3589 OPERATION
Table 8. Inductors for Step-Down Switching Regulators 2 and 3
MANUFACTURERS Coilcraft PART NUMBER XPL4020-102ML XPL4020-152ML XPL4020-472ML SD14-1R2-R SD14-3R2-R SD25-3R3-R CDRH5D16NP-4R7N CDRH38D16RHPNP-3R3M VLF5014ST-2R2N2R3 VLCF5020T-2R7N2R2-1 VLCF5020T-3R3N2R0-1 1124BS-2R4N 1124BS-3R3N H-DI-0520-3R3 H-DI-0520-4R7 H-DI-0630-3R8 H-DI-0630-4R7 744043004 744052002 7440530047 744042003 7440430022 VALUE (H) 1.0 1.5 4.7 1.2 3.2 3.3 4.7 3.3 2.2 2.7 3.3 2.4 3.3 3.3 4.7 3.8 4.7 4.7 2.5 4.7 3.3 2.2 DCR () 0.029 0.036 0.130 0.034 0.066 0.038 0.064 0.059 0.073 0.083 0.096 0.065 0.074 0.062 0.090 0.040 0.043 0.052 0.030 0.030 0.055 0.023 MAX DC CURRENT (A) 4.00 3.60 1.90 3.35 2.00 2.21 2.05 1.46 2.3 2.2 2 2.30 2.10 2.00 1.80 2.00 1.90 1.55 2.4 2.4 1.95 2.5 SIZE (mm) W x L x H 4.2 x 4.2 x 2.0 4.2 x 4.2 x 2.0 4.2 x 4.2 x 2.0 5.2 x 5.2 x 1.45 5.2 x 5.2 x 1.45 4.8 x 4.8 x 2.5 5.6 x 5.6 x 1.8 4.2 x 4.2 x 1.8 4.8 x 4.6 x 1.4 5.0 x 5.0 x 2.0 5.0 x 5.0 x 2.0 4.5 x 4.7 x 1.8 4.5 x 4.7 x 1.8 5.3 x 5.3 x 2.0 5.3 x 5.3 x 2.0 6.3 x 6.3 x 3.0 6.3 x 6.3 x 3.0 5.0 x 5.0 x 3.0 5.8 x 5.8 x 1.8 5.8 x 5.8 x 2.8 4.8 x 4.8 x 1.8 4.8 x 4.8 x 2.8
Cooper
Sumida TDK
TOKO Tokin
Wurth
The value of R1 plays a role in setting the dynamics of the buck-boost voltage mode control loop. In general, a larger value for R1 will increase stability but reduce the speed of the transient response. A good starting point is to choose R1 equal to 1M and calculate the value of R2 needed to set the target output voltage. If a large output capacitor is used, the bandwidth of the converter is reduced and R1 may be reduced to improve transient response. If a large inductor or small output capacitor is used then a larger R1 should be used to bring the loop toward more stable operation. Modes of Operations Table 9 shows the I2C command registers used to control the operating modes of the LTC3589 buck-boost converter. When command register SCR1 bit 6 is LOW, the LTC3589 buck-boost switching regulator operates in a fixed frequency pulse width modulation mode using voltage mode feedback control. A proprietary switching algorithm allows
the converter to transition between buck, buck-boost, and boost modes without discontinuity in inductor current or loop characteristics. The switch topology is shown in the application circuit in Figure 4.
Table 9. Buck-Boost Command Register Settings
COMMAND REGISTER[BIT] SCR1[6] OVEN[3] SCR2[3] VALUE 0* 1 0* 1 0* 1 SETTING Continuous Mode Burst Mode Operation Disable Enable Wait for Output Below 300mV Before Enable Enable Immediately
* Denotes Default Power-On Value
When the input voltage is significantly greater than the output voltage, the buck-boost converter operates in buck mode. Switch D turns on continuously and switch C remains off. Switches A and B are pulse width modulated to produce the required duty cycle to support the output
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LTC3589 OPERATION
regulation voltage. As the input voltage decreases, switch A remains on for a larger portion of the switching cycle. When the duty cycle reaches approximately 85%, the switch pair AC begins turning on for a small fraction of the switching period. As the input voltage decreases further, the AC switch pair remains on for longer durations and the duration of the BD phase decreases proportionately. As the input voltage drops below the output voltage, the AC phase will eventually increase to the point that there is no longer any BD phase. At this point, switch A remains on continuously while switches CD operate as a boost converter to regulate the desired output voltage. The buck-boost is set to Burst Mode operation by writing a 1 to command register SCR1 bit 6. Using Burst Mode operation at light loads improves efficiency and reduces standby current at zero loads. In Burst Mode operation, the inductor is charged with bursts of fixed peak amplitude current pulses. The current pulses are repeated as often as necessary to maintain the target output voltage. The maximum output current that can be supplied in Burst Mode operation is dependent upon the input and output voltage. Typically IOUT(MAX) in Burst Mode operation is equal to: 0.15 * VIN I OUT(MAX) = (A) VOUT + VIN If the buck-boost load exceeds the maximum Burst Mode current capability then the output rail will lose regulation and the power good comparator will indicate a fault condition. When the LTC3589 buck-boost is not enabled, a 2k pull down resistor is connected between BB_OUT and ground. Current Limit Operation The LTC3589 buck-boost regulator has current limit circuits to limit forward current through the A switch and reverse current through the D switch. The primary forward current limit circuit injects a small fraction of the inductor current into the feedback node whenever the inductor current exceeds 2.5A (typical). Forcing the current into the feedback node in the high gain feedback circuit has the effect of lowering the output voltage until the average current in switch A is equal to the current limit. The average limit uses the error amplifier in its active linear state so once the fault condition is removed the recovery is smooth with little overshoot. A hard short on the output of the buck-boost will cause the inductor current to exceed the 2.5A average current limit. A second current limit turns off switch A in the event peak inductor current reaches 3A (typical). The instantaneous forward current limit provides extra protection in the event of a sudden hard short. The reverse current comparator on the D switch monitors the current entering the BB_OUT pin. When this current exceeds 500mA (typical) switch D will turn off for the remainder of the switching cycle. This feature protects the buck-boost converter from excessive reverse current if the buck-boost output is held above the regulation point by an external source. Soft-Start The buck-boost converter has an internal voltage mode soft-start circuit that ramps the buck-boosts error amp reference from 0V to 800mV at a rate of 2mV/s. During soft-start, the converter is regulating to the ramping reference and will respond to output load transients during soft-start. During soft-start the buck-boost converter is forced into continuous mode operation regardless of the state of the SCR1 command register. Inductor Selection Inductor selection criteria for the buck-boost are similar to those given for the step-down switching regulators. The buck-boost converter is designed to work with inductors in the range of 1H to 3.3H. For most applications use a 1.5H inductor. Choose an inductor with a DC current rating
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LTC3589 OPERATION
Table 10. Inductors for Buck-Boost Switching Regulator
MANUFACTURERS Coilcraft PART NUMBER XPL4020-152ML XPL4020-222ML XPL4020-332ML LPS6225-332ML LPS6225-472ML SD14-1R5-R SD14-2R0-R SD14-2R5-R SD14-3R2-R SD25-3R3-R CDRH5D16NP-3R3N CDRH5D16NP-4R7N VLF5014ST-2R2N2R3 VLCF5020T-2R7N2R2-1 VLCF5020T-3R3N2R0-1 1124BS-1R8N 1124BS-3R3N H-DI-0520-3R3 H-DI-0630-3R8 744052002 7440420027 744053003 7440530047 VALUE (H) 1.5 2.2 3.3 3.3 4.7 1.5 2.0 2.5 3.2 3.3 3.3 4.7 2.2 2.7 3.3 1.8 3.3 3.3 3.8 2.5 2.7 3.0 4.7 DCR () 0.036 0.060 0.085 0.055 0.065 0.039 0.045 0.060 0.066 0.038 0.045 0.064 0.073 0.083 0.096 0.056 0.074 0.062 0.040 0.030 0.047 0.024 0.030 MAX DC CURRENT (A) 3.60 2.60 2.40 3.50 3.00 2.91 2.56 2.29 2.00 2.21 2.60 2.05 2.3 2.2 2 2.70 2.10 2.00 2.00 2.4 2.2 2.8 2.4 SIZE (mm) W x L x H 4.2 x 4.2 x 2.0 4.2 x 4.2 x 2.0 4.2 x 4.2 x 2.0 6.0 x 6.0 x 2.0 6.0 x 6.0 x 2.0 5.2 x 5.2 x 1.45 5.2 x 5.2 x 1.45 5.2 x 5.2 x 1.45 5.2 x 5.2 x 1.45 4.8 x 4.8 x 2.5 5.6 x 5.6 x 1.8 5.6 x 5.6 x 1.8 4.8 x 4.6 x 1.4 5.0 x 5.0 x 2.0 5.0 x 5.0 x 2.0 4.5 x 4.7 x 1.8 4.5 x 4.7 x 1.8 5.3 x 5.3 x 2.0 6.3 x 6.3 x 3.0 5.8 x 5.8 x 1.8 4.8 x 4.8 x 1.8 5.8 x 5.8 x 2.8 5.8 x 5.8 x 2.8
Cooper
Sumida TDK
TOKO Tokin Wurth
at least two times larger than the maximum load current to ensure that the inductor does not saturate during normal operation. If output short circuit is a possible condition, the inductor should be rated to handle the maximum peak current specified for the buck-boost converter. Table 9 shows several inductors that work well with the LTC3589 buck-boost regulator. Capacitor Selection Low ESR ceramic capacitors should be used at both the output and input supply of the buck-boost switching regulator. Only X5R or X7R ceramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types.
A 22F capacitor is sufficient for the buck-boost switching regulator output. For good transient response and stability the output capacitor should retain at least 10F of capacitance over operating temperature and bias voltage. Place at least 4.7F decoupling capacitance as close as possible to PVIN4 pin. Refer to Table 11 for recommended ceramic capacitor manufacturers.
Table 11. Ceramic Capacitor Manufacturers
AVX Murata Taiyo Yuden Vishay Siliconix TDK www.avxcorp.com www.murata.com www.t-yuden.com www.vishay.com www.tdk.com
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LTC3589 OPERATION
SLEWING DAC REFERENCE OPERATION Controlling the DAC References The three LTC3589 step-down switching regulators and linear regulator LDO2 have programmable DAC reference inputs. Each DAC is programmable from 0.3625V to 0.75V in 12.5mV steps: VOUT = 1+ R1 * (0.3625 + BxDTVx * 0.0125)(V) R2 Setting and Slewing the DAC Outputs The 5-bit word in dynamic target voltage command registers B1DTV1, B2DTV1, B3DTV1, and L2DTV1 programs reference voltage V1. The 5-bit word in command registers B1DTV2, B2DTV2, B3DTV2, and L2DTV2 programs reference voltage V2. A resistor divider network on the output and feedback pins of the regulators set their output voltage. A 0 or 1 to the odd bits of voltage change control register VCCR selects DAC output voltages V1 or V2 respectively. A slew of the DAC is initiated by writing a 1 to an even bit of register VCCR. The DAC output will slew to either voltage, V1 or V2, as selected by the even bits of register VCCR. Slew begins when the I2C STOP condition is detected. At the end of the slewing operation the GO bits in command register VCCR are cleared. The slew rate for each regulator is set in the ramp rate control register VRRCR. Each DAC has independent output voltage registers, voltage register select, and slew rate and start controls. The regulators do not have to be enabled to change the DAC outputs. The VSTB pin is used to set the DAC controlled output rails to a low power standby condition. When VSTB is driven HIGH, all four of the DAC references will immediately slew to V2. To use VSTB to set the rails to standby voltage, select V1 for normal rail voltages and V2 for standby rail voltages. Drive VSTB high to immediately slew all the DAC outputs to V2. When VSTB is driven LOW, the DAC outputs will slew to V1. The default power up value of all the dynamic target voltage registers is 11001 corresponding to a DAC output voltage of 0.675V. The DTV registers may be reprogrammed prior to initiating a power-up sequence or at any time for dynamic slewing. When a step-down switching regulator output is slewing down its mode is automatically switched to forced continuous to enable the regulator to sink current. When LDO2 is slewing down, a 2k pull down is connected to its output.
The DAC references may be commanded to independently slew between two voltages at one of four selectable slew rates. Table 12 summarizes the command registers used to control slewing DAC operation.
Table 12. Slewing DAC Command Register Control Summary
COMMAND REGISTER[BIT] VCCR[0], VCCR[2], VCCR[4], VCCR[6] FUNCTION Voltage Change Control Register G0 / Slew Write a 1 to Initiate a Slew to the Voltage Selected in VCCR[1], VCCR[3], VCCR[5], VCCR[7] Respectively. Bits are Reset to 0 at the End of the Slew Operation. VCCR[1], VCCR[3], VCCR[5], VCCR[7] Voltage Change Control Register Dynamic Target Select Write a 0 to Select Voltage V1 Stored in Registers B1DTV1[4-0], B2DTV1[4-0], B3DTV1[4-0], L2DTV1[4-0]. Write a 1 to Select Voltage V2 in Registers B1DTV2[4-0], B2DTV2[4-0], B3DTV2[4-0], L2DTV2[4-0]. B1DTV1[4-0], B2DTV1[4-0], Dynamic Target Voltage 1 B3DTV1[4-0], L2DTV1[4-0] Five Bits Corresponding to V1 Output from Each DAC. B1DTV1[5], B2DTV1[5], B3DTV1[5], L2DTV1[5] PGOOD Mask Write a 1 to Continue Normal PGOOD Operation When Slewing. Write a 0 to Force PGOOD to Pull Low During Slew. B1DTV2[4-0], B2DTV2[4-0], Dynamic Target Voltage 2 B3DTV2[4-0], L2DTV2[4-0] Five Bits Corresponding to V2 Output from Each DAC. VRRCR[1-0], VRRCR[3-2], VRRCR[5-4], VRRCR[7-6] Voltage Ramp Rate Control Two Bits That Set the DAC Output Slew Rate for Step-Down Switching Regulator and LDO2.
3589p
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LTC3589 OPERATION
Table 13 shows command register and feedback divider settings to enable slewing step-down switching regulator 1 between 1.2V and 1V in 70s. The voltage ramp rate control register bits VRRCR[1:0] are set to 10 which selects a ramp rate of 1.75mV/s at the DAC output. The slew rate at the regulator output is a function of the feedback resistor divider gain. In this example, the slew is equal to 1.75 * (1 + 301/499) = 2.8mV/s. Therefore, a slew of 200mV will take 70s. To initiate a change from 1.2V to 1V write 11 to voltage change control register bits VCCR[1:0]. VCCR[1] selects target register B1DTV2 to set the regulator reference input to 0.625V. VCCR[0] set to 1 initiates the dynamic slew to go to the new voltage. To slew back to 1.2V write 01 to command register bits VCCR[1:0].
Table 13. Dynamic Slewing Example for Step-Down Switching Regulator 1
COMMAND REGISTER VRRCR[1:0] VCCR[1] B1DTV1[4:0] B1DTV2[4:0] VOUT =1.2V VOUT =1V
is activated by the PWR_ON pin. When the controller enters the PUP state the open drain WAKE pin releases HIGH. The WAKE pin is typically used to enable the first regulator in a start-up sequence. The pushbutton state will stay in PUP for five seconds before transitioning to the power-on (PON) state. Before leaving PUP the PWR_ON pin must be , brought HIGH by the application to indicate that the system rails are correct. If PWR_ON is not active at the end of five seconds the pushbutton controller will continue directly through PON to the power-down (PDN) state and pull the WAKE pin down. Three events will cause the pushbutton to leave the PON state: 1) lowering the PWR_ON pin, 2) forcing a hard reset by holding the ON pin LOW for five seconds, and 3) a fault condition is detected. Fault conditions are low VIN, device over temperature, or extended undervoltage of one of the regulator outputs. All regulator enables, the ON input, and PWR_ON signals are inhibited for one second while in the PDN state. After one second in PDN the pushbutton controller returns to POFF .
01 0
11111 10101
01 1
11111 10101
Dynamic Slew Rate Select DTV Resistor Divider Shown in Figure 3 R1 = 301k R2 = 499k
PUP PB400ms OR PWR_ON 5 SEC
POFF
PON FAULT OR PWR_ON PDN
3589 F05
PUSHBUTTON OPERATION
1 SEC
State Event Diagram Figure 5 shows the LTC3589 pushbutton state diagram. Upon first power application to VIN an internal power-on reset circuit puts the pushbutton into power-down (PDN) state and initiates a one second timer. Status pin RSTO is pulled LOW until one second is timed out and the alwaysalive LDO1 has indicated power good status. After the one second interval the pushbutton circuit will transition to the power-off (POFF) state. The pushbutton will not leave the POFF state and enter the power-up state (PUP) until ON is held LOW for at least 400ms (PB400ms) or until PWR_ON
POR
Figure 5. Pushbutton Controller State Diagram
PBSTAT Operation PBSTAT goes LOW 50ms after the initial pushbutton application (ON LOW) and will stay LOW for a minimum of 50ms. PBSTAT will go HIGH coincident with ON going HIGH unless ON goes HIGH before the 50ms minimum on-time.
3589p
27
LTC3589 OPERATION
Power-Up Using the Pushbutton When in the POFF state, the LTC3589 is in complete shutdown except the always active LDO1 and regulators enabled with the keep-alive control bits. Pull the ON pin to ground with a pushbutton for 400ms to begin a power-up sequence with the WAKE pin tied to an enable pin. Drive PWR_ON high within five seconds to signal the LTC3589 to remain in the power-on state.
ON(PB) PBSTAT 400ms WAKE PWR_ON <5 SEC C/P CONTROL
3589 F06
ON(PB) PBSTAT WAKE PWR_ON 50ms 5 SEC C/P CONTROL 50ms
3589 F08
Figure 8. Power-Up and Down Using PWR_ON Pin
Hard Reset Using the Pushbutton When the ON pin is pulled LOW for five seconds, a hard reset is initiated. At the end of five seconds, WAKE is pulled LOW, the I2C command registers are reset to POR states, enable pin states are ignored, and the one second power-down timer is started. During the power-down time, the enables continue to be ignored to allow the regulator outputs to discharge. The RSTO pin is pulled LOW for the power-down time to indicate a pushbutton hard reset occurred. If the PWR_ON pin is LOW at the end of the one second power-down time, the LTC3589 will remain in sleep mode. If PWR_ON is HIGH at the end of one second and there are no fault conditions, the LTC3589 will power-up in the same way shown in Figure 8.
ON(PB) 50ms PBSTAT WAKE PWR_ON RSTO 5 SEC C/P CONTROL 1 SEC
3589 F09
Figure 6. Power-Up Using the Pushbutton
Power-Down Using the Pushbutton The pushbutton power-down operation is performed by the system microprocessor by monitoring the PBSTAT pin. Once in the PON state, the system controller is responsible for deciding what action to take with a pushbutton event. When the ON pin is held LOW for a 50ms debounce period, the PBSTAT pin is pulled LOW. The system controller should monitor the PBSTAT pin to determine the pushbutton has been pushed. If the controller decides that a power down is desired, then it should drive the PWR_ON pin LOW.
ON(PB) 50ms PBSTAT WAKE 50ms PWR_ON C/P CONTROL
3589 F07
<5 SEC
Figure 9. Hard Reset Using the Pushbutton
Figure 7. Power Down Using Pushbutton
Hard Reset Due to a Fault Condition Power-Up and Down Using PWR_ON Pin An alternate power-up method is to drive the PWR_ON pin to a HIGH state. After a delay of 50ms from the PWR_ON signal, the WAKE pin will pull HIGH to drive regulator enable pins. When PWR_ON is HIGH for five seconds, the sequence controller will enter the PON state. To power down, drive the PWR_ON pin LOW. WAKE will pull down 50ms later. A hard reset due to VIN undervoltage, extended undervoltage of an output rail, or an over temperature condition initiates a hard shutdown of the LTC3589. When the fault occurs, wake is pulled LOW, the I2C command registers are reset to POR states, enable pin inputs are ignored, and the one second power down timer is started. During the powerdown time, the enables continue to be ignored to allow the
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LTC3589 OPERATION
regulator outputs to discharge. If the PWR_ON pin is LOW at the end of the power-down time, the LTC3589 will remain in sleep mode with just the always-active LDO operating. If PWR_ON is HIGH at the end of one second and the fault condition has cleared, the LTC3589 will power-up in the same way shown in Figure 8. Neither IRQ nor the status registers are cleared by the fault induced shutdown.
FAULT ON(PB) PBSTAT WAKE PWR_ON IRQ CLIRQ
3589 F10
brings up the WAKE pin that is tied to EN1 and EN3 to enable step-down switching regulators 1 and 3. The output of regulator 1 is tied to EN2 and EN4 that enables stepdown switching regulator 2 and the buck-boost switching regulator 4. The output of step-down switching regulator 2 is tied to EN_LDO2 and EN_LDO3 to enable LDO2, LDO3 and LDO4. Within five seconds of WAKE going HIGH, the microprocessor or microcontroller must drive PWR_ON HIGH to tell LTC3589 that rails are good and to stay in the power-on state. Figure 12 shows the start-up timing for the application shown in Figure 11. There is a 200s (typical) delay between the enable pin and the internal enable signal to each regulator.
WAKE V1 V3 0.5V 200s 1.2V 1V 200s 1.8V 3.3V
<1 SEC C/P CONTROL
Figure 10. Hard Reset Due to a Fault Condition
ENABLE AND POWER-ON SEQUENCING Enable Input Pin Operation The regulator enable input pins facilitate pin-strapping an output rail to the enable pin of the next regulator in the desired sequence. The regulator enable inputs normally have a 0.8V (typical) input threshold. If any enable is driven HIGH, the remaining enable input thresholds switch to a more accurate 500mV (typical) threshold. Figure 11 shows an application circuit for a typical pinstrapped start-up sequence. Holding ON LOW for 400ms
V2 V4 LDO2 LDO3 LDO4
0.5V
1.2V 200s 1.8V 2.8V
3589 F12
Figure 12. Pin Strap Sequencing Timing
Keep-Alive Operation For systems which require an active supply rail when in system standby, any of the three LTC3589 step-down switching regulators or LDO2 may be kept alive regardless of the status of PWR_ON and WAKE. Writing a 1 to a regulator's keep-alive bit in its dynamic target voltage register will keep a regulator alive when the LTC3589 is in standby mode. A regulator with its keep-alive bit set will stay enabled until the bit is reset writing the bit LOW, resetting the LTC3589 with a push button hard reset, or a fault condition (UVLO, PGOOD time out, or thermal shutdown) occurs. PGOOD and fault status are reported in the IRQSTAT and PGSTAT registers and on the IRQ and PGOOD pins for keep-alive regulators when PWR_ON and WAKE are LOW.
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LTC3589 EN1 EN2 EN3 EN4 EN_LDO2 EN_LDO34 ON PWR_ON PWR_ON WAKE SW1 SW2 SW3 BB_OUT LDO2 LDO3 LDO4
3589 F11
1V TO 1.2V 1.8V 0.8V TO 1V 3.3V 1.2V 1.8V 2.8V
Figure 11. Pin Strap Start-Up Sequence Application Circuit
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LTC3589 OPERATION
Software Control Mode Once a power-up sequence is completed each regulator may be enabled and disabled individually by the system as needed for power mode requirements. Setting the output voltage enable command register bit OVEN[7] HIGH disconnects each regulator from its enable pin so control is solely through the OVEN command register. To enter software control mode, set command bit OVEN[7] HIGH and the desired enable bits in OVEN[6:0] HIGH. Any of the regulators enabled in OVEN[6:0] will stay on regardless of the state of their enable pins when OVEN[7] is HIGH. Setting the regulator enable bits and the software control bit in OVEN[7] may occur on the same I2C start-stop sequence. A normal shutdown using PWR_ON, OVEN register to 0x00 to ensure all regulators are shut off. FAULT DETECTION, SHUTDOWN, AND REPORTING The LTC3589 monitors VIN, output rail voltages and internal die temperature. A warning condition is indicated when VIN is less than 2.9V and when internal die temperature approaches the thermal shutdown temperature. A fault condition occurs when VIN is less than 2.6V, any regulator output is 8% low for 14ms, or the internal die temperature is HIGH. Warning and fault states are reported via the IRQ, PGOOD, and RTSO pins. Specific fault states are read via the I2C serial port status registers IRQSTAT and PGSTAT. RSTO Pin Function The RSTO (reset output) pin is an open drain output for use as a power-on reset signal. It is pulled LOW at initial power until LDO1 is within 8% of its target and the initial one second start-up timer is finished. RSTO remains HIGH during normal operation and will be pulled low if LDO1 loses regulation for more than 25s or a pushbutton hard reset is initiated. Figure 13 shows a initial power up for the RSTO pin. If VIN is not above its under voltage thresholds at the end of the 1 second start up time, the IRQ pin will be pulled LOW and an under voltage bit will be set in the IRQSTAT status register.
VIN 2.7V LDO1 RSTO 1 SEC INITIAL POWER-UP LDO1 UNDERVOLTAGE
3589 F13
>25s 14ms
Figure 13. Initial Power-Up and LDO1 Undervoltage RSTO Timing
PGOOD Pin and PGSTAT Status Register Function Each LTC3589 regulator has an internal power good output that is active whenever the regulators feedback pin is closer than -8% (typical) from its input reference voltage. If any of the internal power good signals indicate a low voltage for longer than 25s (typical), the PGOOD pin is pulled LOW and the appropriate bit in the PGSTAT status register (Table 14) is set.
Table 14. PGSTAT Read Only Register Bit Definitions
PGSTAT[BIT] VALUE SETTING LDO1_STBY Output Low LDO1_STBY Output Good Step-Down Switching Regulator 1 Output Low Step-Down Switching Regulator 1 Output Good Step-Down Switching Regulator 2 Output Low Step-Down Switching Regulator 2 Output Good Step-Down Switching Regulator 3 Output Low Step-Down Switching Regulator 3 Output Good Buck-Boost Regulator 4 Output Low Buck-Boost Regulator 4 Output Good LDO2 Output Low LDO2 Output Good LDO3 Output Low LDO3 Output Good LDO4 Output Low LDO4 Output Good
0 1 2 3 4 5 6 7
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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LTC3589 OPERATION
Figure 14 shows the PGOOD pin and PGSTAT status register timing. When no regulator is enabled, the PGOOD pin is pulled LOW and PGSTAT bits are LOW. PGOOD and the PGSTAT bits are HIGH 250s after the last enabled regulator is within 7% of its target.
WAKE HIGH AFTER 1sec IF PWR_ON HIGH 1sec
fault condition initiates a hard shutdown reset. Figure 15 shows undervoltage warning and fault detection levels.
FAULT VIN UNDERVOLTAGE
WARNING
WAKE ENx 200s VOUTx 250s PGOOD IRQ ENABLE UNDERVOLTAGE 25s 25s
2.55V
2.65V
2.9V
3V
VIN
3589 F15
Figure 15. UV Detection Hard Reset and Warning Levels
DISABLED IF WAKE LOW
250s 250s 14ms
An undervoltage warning sets register bit IRQSTAT[4] and pulls the IRQ pin LOW. To minimize standby quiescent current the UVLO and thermal sensor circuits are disabled when all the regulators are off.
EXTENDED UNDERVOLTAGE (FAULT)
DISABLE
3589 F14
Thermal Shutdown Fault and Warning Similar to the VIN undervoltage detection circuits the over temperature detection circuits check for warning and fault levels. An over temperature fault will initiate a fault induced shutdown. An over temperature warning sets register bit IRQSTAT[6] and pulls the IRQ pin LOW. IRQ Pin and IRQSTAT Status Register Function The IRQ pin and IRQSTAT status register report PGOOD timeout fault, VIN undervoltage warning and fault, and high temperature warning and fault. Table 15 shows the meaning of the IRQSTAT read only status register bits.
Table 15. IRQSTAT Read Only Register Bit Definitions
IRQSTAT[BIT] VALUE SETTING PGOOD Timeout Fault (PGOOD low > 14ms) VIN Under Voltage Warning (VIN < 2.9V) VIN Under Voltage Fault (VIN < 2.6V) Thermal Limit Warning (TJ > 130C) Thermal Limit Fault (TJ > 150C)
Figure 14. PGOOD Pin and PGSTAT Status Register Timing
If any enabled regulator output falls more than 8% low for longer than 25s PGOOD is pulled LOW and a status bit is set in the PGSTAT register. The PGOOD pin and PGSTAT status bit remain LOW for as long as the low voltage condition persists plus 250s. An extended low output rail causing the PGOOD pin to be LOW for longer than 14ms defines a PGOOD timeout fault condition that triggers a hard reset if not masked in I2C register bit SCR2[7]. During a dynamic voltage slew, PGOOD is pulled LOW unless bit 5 in the dynamic target voltage register for each regulator is set HIGH. When SCR2[7] is HIGH, PGOOD remains in normal operation. The status register PGSTAT is unaffected by a dynamic voltage slew. Undervoltage Detection The LTC3589 under voltage (UV) detection circuit will output a fault condition, locking out regulator operation, until VIN reaches 2.7V (typical). Once VIN is above the fault threshold the LTC3589 will operate normally until VIN drops to 2.6V (typical). When VIN drops below 2.6V, the
3 4 5 6 7
1 1 1 1 1
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LTC3589 OPERATION
Figure 16 shows the timing of the IRQ and IRQSTAT status register following a warning (VIN <2.9V or high temperature warning) event. When a warning occurs, IRQ is latched LOW and bit IRQSTAT[4] or IRQSTAT[5] is set. IRQ remains LOW until I2C command register CLIRQ is written. The status bits in the IRQSTAT register will remain active until CLIRQ is accessed and the warning condition has passed.
TSD OR UV WARNING IRQ IRQSTAT CLIRQ
3589 F16
Fault Induced Shutdown Any of the three fault conditions will initiate a hard reset shutdown triggering the following events: 1) A bit corresponding to the fault is set in status register IRQSTAT, 2) IRQ and WAKE pins are pulled LOW, 3) enable pin inputs are ignored and the regulators are disabled, 4) all enable bits and software control mode bit in the output voltage enable OVEN command register are cleared, and 5) the pushbutton controller is sent to the PDN state for one second and then to POFF Re-enabling of regulators is . inhibited until both the fault condition and the one second time out have passed to allow regulator outputs sufficient time to discharge. When one second timeout and the fault condition are both passed, if PWR_ON is HIGH, WAKE will come up and the LTC3589 will respond to any enable pins that are also HIGH. I2C OPERATION I2C Interface The LTC3589 communicates with a bus master using the standard I2C 2-wire interface. The two bus lines, SDA and SCL, must be HIGH when the bus is not in use. External pull-up resistors or current sources, such as the LTC1694 SMBus accelerator, are required on these lines. The LTC3589 is both a slave receiver and slave transmitter. The I2C control signals, SDA and SCL are scaled internally to the DVDD supply. DVDD should be connected to the same power supply as the bus pull-up resistors. The I2C port has an under voltage lockout on the DVDD pin. When DVDD is below approximately 1V, the I2C serial port is reset to power-on states and registers are set to default values.
Figure 16. IRQ and IRQSTAT Status Register Warning Timing
Figure 17 shows the timing of the IRQ pin and IRQSTAT status register following a fault induced hard shutdown event. When a fault occurs, IRQ is latched LOW and bit IRQSTAT[3], IRQSTAT[5], or IRQSTAT[7] is set. IRQ remains LOW until I2C command register CLIRQ is accessed. When the CLIRQ command has been issued, the IRQSTAT status bit remains set for the one second enable inhibit time or as long as the fault condition persists, whichever is longer.
TSD, UV, OR PGOOD FAULT IRQ 1 SEC IRQSTAT CLIRQ
3589 F17
1 SEC
Figure 17. IRQ and IRQSTAT Status Register Fault Timing
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LTC3589 OPERATION
I2C Bus Speed The I2C port operates at speeds up to 400kHz. It has built-in timing delays to ensure correct operation when addressed from an I2C compliant master device. It also contains input filters designed to suppress glitches should the bus become corrupted. I2C START and STOP Conditions A bus master signals the beginning of communications by transmitting a START condition. A START condition is generated by transitioning SDA from HIGH to LOW while SCL is HIGH. The master may transmit either the slave write or the slave read address. Once data is written to the LTC3589, the master may transmit a STOP condition that commands the LTC3589 to act upon its new command set. A STOP condition is sent by the master by transitioning SDA from LOW to HIGH while SCL is HIGH. The bus it then free for communication with another I2C device. I2C Byte Format Each byte sent to or received from the LTC3589 must be 8 bits long followed by an extra clock cycle for the acknowledge bit. The data should be sent to the LTC3589 most significant bit (MSB) first. I2C Acknowledge The acknowledge signal is used for handshaking between the master and the slave. When the LTC3589 is written to (write address), it acknowledges its write address and subsequent register address and data bytes. When reading from the LTC3589, it acknowledges its read address and 8-bit status byte. An acknowledge pulse (active LOW) generated by the LTC3589 lets the master know that the latest byte of information was transferred. The master generates the clock cycle and releases the SDA line (HIGH) during the acknowledge
SDA tSU, DAT tLOW SCL tHD, STA START CONDITION tr tHIGH tf REPEATED START CONDITION tSP STOP START tHD, DAT tHD, STA tHD, STA tBUF tSU, STO
3589 F18
Figure 18. LTC3589 I2C Timing
ADDRESS 0 START SDA 0 1 1 0 1 0 0 0 ACK 1 1 0 1 0 0 WR
SUB-ADDRESS S7 S6 S5 S4 S3 S2 S1 S0
DATA D7 D6 D5 D4 D3 D2 D1 D0
SUB-ADDRESS S7 S6 S5 S4 S3 S2 S1 S0
DATA D7 D6 D5 D4 D3 D2 D1 D0 STOP
ACK
ACK
ACK
ACK
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
3589 F19
Figure 19. LTC3589 I2C Serial Port Multiple Write Pattern
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LTC3589 OPERATION
clock cycle. The LTC3589 pulls down the SDA line during the write acknowledge clock pulse so that it is a stable LOW during the HIGH period of this clock pulse. I2C Slave Address The LTC3589 responds to factory programmed read and write addresses. The write address is 0x68. The read address is 0x69. The LSb of the address byte, known as the read/write bit, is 0 when writing data to the LTC3589 and 1 when reading from it. I2C Sub-Addressed Writing The LTC3589 has 14 command registers for control inputs. They are accessed by the I2C port via a sub-addressed writing system. Each write cycle of the LTC3589 consists of a series of three or more bytes beginning with the LTC3589 write address. The second byte is the sub-address of the command register being written to. The sub-address is a pointer to the register where the data in the third byte will be stored. The third byte is the data to be written to the just-received sub-address. Continue alternating subaddress and data bytes to write multiple registers in a single START sequence. I2C Bus Write Operation The master initiates communication with the LTC3589 with a START condition and the LTC3589's write address. If the address matches that of the LTC3589, the LTC3589 returns an acknowledge pulse. The master should then deliver the sub-address. Again the LTC3589 acknowledges and the cycle is repeated for the data byte. The data byte is
ADDRESS 0 START SDA 0 1 1 0 1 0 0 0 ACK 1 1 0 1 0 0 WR SUB-ADDRESS S7 S6 S5 S4 S3 S2 S1 S0 START ACK 0 1 1
transferred to an internal holding latch upon the return of its acknowledge by the LTC3589. Continue writing sub-address and data pairs into the holding latches. Addressing the LTC3589 is not required for each sub-address and data pair. If desired a REPEAT-START condition may be initiated by the master where another device on the I2C bus is addressed. The LTC3589 remembers the valid data it has received. Once all the devices on the I2C have been addressed and sent valid data and a global STOP has been sent, the LTC3589 will update its command latches with the data it has received. I2C Sub-Addressed Reading The LTC3589 I2C interface supports random address reading of the I2C command and status registers. Before reading a register, the registers sub-address must be written. Send a START condition followed by the LTC3589 write address followed by the sub-address of the register to be read. The sub-address is now stored as a pointer to the register. Send a REPEAT-START condition followed by the LTC3589 read address. Following the acknowledgment of its read address the LTC3589 returns one bit of information for each of the next 8 clock cycles. A STOP condition is not required for the read operation. The read sub-address is stored until a new sub-address is written. Verify the data written to the internal data hold latches prior to committing date to the command registers by reading back the data before sending a STOP condition. Continuously poll a register by repeatedly sending a START condition followed by the LTC3589 read address, and then clocking the data out after the read address acknowledge.
ADDRESS 0 1 0 0 RD DATA R7 R6 R5 R4 R3 R2 R1 R0 STOP 0 1 1 0 1 0 0 1 ACK ACK
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
3589 F20
Figure 20. LTC3589 I2C Serial Port Read Pattern
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LTC3589 OPERATION
I2C Command and Status Registers Table 16 and Table 17 show the LTC3589 I2C command and status registers. System control register (SCR1) sets the operating modes of the switching regulators. Each step-down switching regulator has pulse-skipping, Burst Mode operation, or forced continuous operation. The buck-boost switching regulator can be put in continuous or Burst Mode operation. The output voltage enable (OVEN) command register controls the individual enables of each regulator. When OVEN[7] is set to a logic LOW value, bits OVEN[6-0} are ORed with their respective enable pins. When OVEN[7] is HIGH, the input pins EN1, EN2, EN3, EN4, EN_LDO2, and EN_LDO34, are ignored and the LTC3589 regulators respond only to the OVEN register. When the regulators are configured in a hard wired power-up sequence, setting OVEN[7] allows software control of individual regulators. When the PWR_ON pin is pulled LOW all bits in the OVEN register are reset to POR state of 0x00. System control register 2 (SCR2) controls the operation of the regulator start-up and regulator power-good (PGOOD) hard shutdown operation. Set command register SCR2[7] to inhibit a hard shutdown of the regulators in the event of an extended low output rail voltage. The low output voltage event is still reported via the IRQ pin and IRQSTAT status register. Set the bits in SCR2[6-0] LOW to force a regulator to ignore its enable until its output has fallen to less than 300mV (typical). If set HIGH, the regulator will enable without waiting for its output to discharge and will not engage the 2k discharge resistor. LDO2 and step-down switching regulators 1 to 3 each have a pair of control bits in the voltage change control register VCCR. The reference select bit selects which of two 5-bit words are used as inputs to the regulators feedback reference DAC inputs. The slew go bit initiates a DAC slew to the voltage selected by the reference select bit. When the slew is complete, the slew go bits are reset LOW. Accessing the CLIRQ command register will clear the IRQ pin and will let the IRQ pin to release HIGH. The pin is cleared when the LTC3589 acknowledges the sub-address. Data written to the CLIRQ command register is ignored. There are eight command registers that are used to store the 5-bit dynamic target voltage input to the feedback reference slewing DACs - B1DTV1, B1DTV2, B2DTV1, B2DTV2, B3DTV1, B3DTV2, L2DTV1 and L2DTV2. The registers ending with V2 use bits 4 through 0 to store the V2 feedback reference voltage for the regulators. The regulators input reference voltage is set to V2 by setting the reference select bits HIGH in VCCR and writing to the go bits in VCCR. The V2 voltage is also selected whenever the VSTB pin is driven HIGH. The registers ending with V1 use bits 4 through 0 to store the V1 feedback voltage reference for the regulators. The regulators input reference voltage is set to V1 voltage by setting the reference select bits LOW in command register VCCR. Whenever a new dynamic target voltage is set, either by changing the 5-bit value or by changing the reference select bits in VCCR, the go bits in VCCR must be written to initiate the dynamic voltage slew. When bit 5 in B1DTV1, B2DTV1, B3DTV1, and L2DTV1 is LOW the PGOOD pin pulls LOW during a dynamic voltage slew. Bits 7 and 6 in B1DTV1 set the switch DV/DT rate for all the step-down switching regulators. Bit 5 in registers B1DTV2, B2DTV2 and B3DTV2 selects the switching frequency of step-down switching regulators 1, 2 and 3. Writing the bit LOW sets the switching frequency to 2.25MHz. Writing the bit HIGH sets the switching frequency to 1.125MHz. The dynamic slew rates of the four feedback reference DACs are independently set using bits in voltage ramp rate command register (VRRCR). The rate shown is the slew of the DAC output as it slews up or down to its target value. The slew rate of the output voltage is scaled by the gain of the resistor divider network that sets the regulator output voltage. For example, a regulator set to an output voltage of 1.2V when the dynamic target voltage reference is 0.75V has a gain of 1.6. Slewing the regulator output from 1.2V to 1V requires slewing the DAC output down 125mV from 750mV to 625mV. With a VRRCR slew rate setting of 01 the slew time of the regulator output is 71s.
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LTC3589 OPERATION
Table 16. LTC3589 Command Register Table
REG NAME B[7] B[6] Buck-Boost Mode: 0= Continuous 1 = Burst Mode 0x10 OVEN Software EN_LDO4 Control Mode: 0 = Enable with Pin or OVEN Register 1 = Enable/ Disable with OVEN Register Only 0x12 SCR2 Mask PGOOD Hard Shutdown: 0 = Allow PGOOD Timeout Hard Shutdown. 1 = Inhibit PGOOD Hard Shutdown. 0x20 VCCR LDO2 Reference Select: LDO4 Startup: LDO3 Startup: LDO2 Startup: Buck-Boost Startup: Step-Down Switching Regulator 3 Startup: 0 = Wait for Output < 300mV Before Enable 1 = Don't Wait and Disable Discharge Resistor. Step-Down Switching Regulator 2 Startup: 0 = Wait for Output < 300mV Before Enable 1 = Don't Wait and Disable Discharge Resistor. Step-Down 0000 0000 Switching Regulator 1 Startup: 0 = Wait for output < 300mV Before Enable 1 = Don't Wait and Disable Discharge Resistor. 0000 0000 Start Step-Down Switching Regulator 1 Slew: 0 = Went 1= GO 1= B1DTV2[4-0]2 0001 1001 B[5] B[4] B[3] B[2] B[1] B[0] DEFAULT 0000 0000 0x07 SCR1 Step-Down Switching Regulator 3 Mode : 0 0 = Pulse-Skipping 0 1 = Burst 1 0 = Forced Continuous EN_LDO3 EN_LDO2 Step-Down Switching Regulator 2 Mode : 0 0 = Pulse-Skipping 0 1 = Burst 1 0 = Forced Continuous EN4 EN3 Step-Down Switching Regulator 1 Mode : 0 0 = Pulse-Skipping 0 1 = Burst 1 0 = Forced Continuous EN2 EN1 0000 0000
0 = Wait for Output < 300mV Before Enable 1 = Don't Wait and Disable Discharge Resistor. Start LDO2 Slew:
0 = Wait for Output < 300mV Before Enable
1 = Don't Wait and Disable 1 = Don't Wait and Disable 1 = Don't Wait Discharge and Disable Resistor. Discharge Discharge Resistor. Resistor. Step-Down Switching Regulator 3 Reference Select: Start Step-Down Switching Regulator 3 Slew: Step-Down Switching Regulator 2 Reference Select:
0 = Wait for Output < 300mV Before Enable
0 = Wait for Output < 300mV Before Enable
Start Step-Down Switching Regulator 2 Slew:
Step-Down Switching Regulator 1 Reference Select: 0= B1DTV1[4-0]
0= 0 = Went L2DTV1[4-0] 1 = GO 1= L2DTV2[4-0] 0x21 CLIRQ 0x23 B1DTV1 Step-Down Switching Regulator Switch DV/DT Control: 00 = 1ns 01 = 2ns 10 = 4ns 11 = 8ns
0 = Went 0= B3DTV1[4-0] 1= GO 1= B3DTV2[4-0]2 PGOOD Mask: 0 = PGOOD Low When Slewing 1 = PGOOD Not Forced Low When Slewing.
0 = Went 0= B2DTV1[4-0] 1= GO 1= B2DTV2[4-0]
Step-Down Switching Regulator 1 Feedback Reference Input (V1)
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LTC3589 OPERATION
Table 16. LTC3589 Command Register Table
0x24 B1DTV2 Keep-Alive Mode: 0 = Normal Shutdown Phase Select: 0 = Clock Phase 1 Step-Down Switching Regulator 1 Clock Rate 0 = 2.25MHz 1 = 1.12MHz Step-Down Switching Regulator 3 Dynamic Reference Slew Rate: 00 = 0.88mV/s 01 = 1.75mV/s 10 = 3.5mV/s 11 = 7mV/s PGOOD Mask: 0 = PGOOD Low When Slewing 1 = PGOOD Not Forced Low When Slewing. 0x27 B2DTV2 Keep-Alive Mode: 0 = Normal Shutdown Phase Select: 0 = Clock Phase 1 Step-Down Switching Regulator 2 Clock Rate 0 = 2.25MHz 1 = 1.125MHz PGOOD Mask: 0 = PGOOD Low When Slewing 1 = PGOOD Not Forced Low When Slewing. 0x2A B3DTV2 Keep-Alive Mode: 0 = Normal Shutdown Phase Select: 0 = Clock Phase 1 Step-Down Switching Regulator 3 Clock Rate 0 = 2.25MHz 1 = 1.125MHz Step-Down Switching Regulator 3 Feedback Reference Input (V2) 0001 1001 Step-Down Switching Regulator 3 Feedback Reference Input (V1) 0001 1001 Step-Down Switching Regulator 2 Feedback Reference Input (V2) 0001 1001 Step-Down Switching Regulator 2 Dynamic Reference Slew Rate: 00 = 0.88mV/s 01 = 1.75mV/s 10 = 3.5mV/s 11 = 7mV/s Step-Down Switching Regulator 1 Dynamic Reference Slew Rate: 00 = 0.88mV/s 01 = 1.75mV/s 10 = 3.5mV/s 11 = 7mV/s 0001 1001 1111 1111 Step-Down Switching Regulator 1 Feedback Reference Input (V2) 1111 1111
1 = Keep-Alive 1 = Clock Phase 2 0x25 VRRCR LDO2 Dynamic Reference Slew Rate: 00 = 0.88mV/s 01 = 1.75mV/s 10 = 3.5mV/s 11 = 7mV/s 0x26 B2DTV1 Unused
Step-Down Switching Regulator 2 Feedback Reference Input (V1)
1 = Keep-Alive 1 = Clock Phase 2 0x29 B3DTV1 Unused
1 = Keep-Alive 1 = Clock Phase 2
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LTC3589 OPERATION
Table 16. LTC3589 Command Register Table
0x32 L2DTV1 Keep-Alive Mode: 0 = Normal Shutdown 1 = Keep-Alive Unused PGOOD Mask: 0 = PGOOD Low When Slewing 1 = PGOOD Not Changed When Slewing. 0x33 L2DTV2 LDO4 Control MODE: 0 = LDO4 Enable with EN_LDO34 1 = LDO4 Enable with OVEN[6] LDO4 Output Voltage: 00 = 2.8V 01 = 2.5V 10 = 1.8V 11 = 3.3V LDO 2 Feedback Reference Input (V2) 0001 1001 LDO 2 Feedback Reference Input (V1) 0001 1001
Table 17. LTC3589 Read Only Status Register Table
REG 0x02 NAME B[7] B[6] B[5] B[4] Near Undervoltage Limit Buck_Boost Status: B[3] B[2] B[1] Unused B[0] Unused IRQSTAT Thermal Limit Hard Shut Down Occurred PGSTAT LDO4 Status: Near Thermal Undervoltage Limit Hard Shut Down Occurred LDO3 Status: LDO2 Status: PGOOD Unused Timeout Hard Shutdown Occurred Step-Down Switching Regulator 3 Status: 0 = VOUT Low 1 = VOUT Good Step-Down Switching Regulator 2 Status: 0 = VOUT Low
0x13
Step-Down Switching Regulator 1 Status: 0 = VOUT Low
LDO1 Status:
0 = VOUT Low 1 = VOUT Good
0 = VOUT Low 1 = VOUT Good
0 = VOUT Low
0 = VOUT Low
0 = VOUT Low
1 = VOUT Good 1 = VOUT Good
1 = VOUT Good 1 = VOUT Good 1 = VOUT Good
THERMAL CONSIDERATIONS AND BOARD LAYOUT Printed Circuit Board Power Dissipation In order to ensure optimal performance and the ability to deliver maximum output power to any regulator, it is critical that the exposed ground pad on the backside of the LTC3589 package be soldered to a ground plane on the board. The exposed pad is the only GND connection for the LTC3589. Correctly soldered to a 2500mm2 ground plane on a double sided 1oz copper board the LTC3589 has a thermal resistance (JA) of approximately 34C/W. Failure to make good thermal contact between the exposed pad on the backside of the package and an adequately sized ground plane will result in thermal resistances far greater than 34C/W.
To ensure the junction temperature of the LTC3589 die does not exceed the maximum rated limit and to prevent over temperature faults, the power output of the LTC3589 must be managed by the application. The total power dissipation in the LTC3589 is approximated by summing the power dissipation in each of the switching regulators and the LDO regulators. The power dissipation in a switching regulator is estimated by: PD(SWX) = (VOUTX * I OUTX )* 100 - Eff 100
Where VOUTX is the programmed output voltage, IOUTX is the load current and Eff is the % efficiency that can
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LTC3589 OPERATION
be measured or looked up in an efficiency table for the programmed output voltage. The power dissipated by an LDO regulator is estimated by: PD(LDOX) = (VIN(LDOX) - V LDOX )* I LDOX Where VLDOX is the programmed output voltage, VIN(LDOX) is the LDO supply voltage, and ILDOX is the output load current. If one of the switching regulator outputs is used as an LDO supply voltage, remember to include the LDO supply current in the switching regulator load current for calculating power loss. With JA of 34C/W and maximum ambient operating temperature of 85C, the power dissipation must be kept under 1.18W so that maximum junction temperature is less than 125C. An example using the equations above with the parameters in Table 18 shows an application that is at the maximum junction temperature of 125C at an ambient temperature of 85C. LDO2, LDO3, and LDO4 are powered by stepdown switching regulator 2 and the buck-boost switching regulator. The total load on those two switching regulators is the sum of the application load and the LDO load. This example is with the LDO regulators at one half rated current and the switching regulators at three quarters rated current.
Table 18. TJ Calculation Example
OUTPUT VIN VOUT APP LOAD 1.2V 1.2V 1.8V 2.5V 1.2V 1.8V 1.25V 3.3V 10mA 100mA 100mA 100mA 1.2A 0.65A 0.75A 0.70A TOTAL LOAD 10mA 100mA 100mA 100mA 1.2A 0.75A 0.75A 0.90A 80% 90% 85% 90% EFF POWER DISS 30mW 60mW 150mW 80mW 290mW 140mW 140mW 300mW 1180mW 125C
Printed Circuit Board Layout When laying out the printed circuit board, the following checklist should be followed to ensure proper operation of the LTC3589: 1. Connect the exposed pad of the package (Pin 41) directly to a large ground plane to minimize thermal and electrical impedance. 2. The switching regulator input supply traces and their decoupling capacitors should be as short as possible. Connect the GND side of the capacitors directly to the ground plane of the board. The decoupling capacitors provide the AC current to the internal power MOSFETs and their drivers. It is important to minimize inductance from the capacitors to the LTC3589 pins. 3. Minimize the switching power traces connecting SW1, SW2, SW3, and buck-boost switch pins SW4AB and SW4CD to the inductors to reduce radiated EMI and parasitic coupling. Keep sensitive nodes such as the feedback pins away from or shielded from the large voltage swings on the switching nodes. 4. Minimize the length of the connection between the step-down switching regulator inductors and the output capacitors. Connect the GND side of the output capacitors directly to the thermal ground plane of the board. 5. Minimize the length of the connection between the buck-boost regulator output (BB_OUT) and the output capacitor. Connect the GND side of the output capacitor directly to the thermal ground plane of the board.
LDO1_VSTB 3.8V LDO2 LDO3 LDO4 VOUT1 VOUT2 VOUT3 VOUT4 1.8V 3.3V 3.3V 3.8V 3.8V 3.8V 3.8V
TOTAL POWER INTERNAL JUNCTION TEMPERATURE AT 85C AMBIENT
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LTC3589 APPLICATIONS INFORMATION
The LTC3589 is optimized to support several families of advanced portable applications processors including the Marvell PXA3xx and PXA168 xscale processors, the Freescale i.MX family including the new i.MX51, the TI OMAP processors utilizing their Smart reflex, and many additional ARM processors. PXA3XX Monahans Processor Support The PXA3XX processors are hardcoded to communicate with a PMIC at specific command register addresses in order to power up the processor supply rails from the low power state. The LTC3589 I2C device address and command register addresses map to PXA3xx command register sub-address requirements. The LTC3589 write address is 0x68. The key command register addresses for PXA3xx support are the Output Voltage Enable (OVEN) register at address 0x10. VCC_APPS/A_EN is mapped to OVEN bit 0 (enable step-down switching regulator 1). VCC_SRAM/S_EN is mapped to OVEN bit 2 (enable stepdown switching regulator 3). The voltage change control register (VCCR) at command register address 0x20 controls the dynamic voltage select and go bits required to command a voltage change and slew when coming out of low voltage standby or sleep modes into run mode. The dynamic target voltage (xxDTV[1,2]) registers map to the mandatory command register addresses. The full register map for the LTC3589 shown in Table 15 and Table 16 supports Monahans, hard-coded I2C commands for start-of-day operation, voltage-change sequence, supply enable, and return-to-D0 state sequence. The LTC3589 does not specifically reference the Monahans SYS_EN and PWR_EN enable pins but supports these signals with individual enable input pins EN[1-4] and EN_LDO[2,3] that should be hard-wired to SYS_EN or PWR_EN as required for proper system level power sequencing. The LTC3589 RSTO signal is used to drive the Monahans hard reset signal nRESET and is based on the state of the always-active regulator output LDO1_STBY and by a pushbutton hard reset request. The release of the RSTO output is delayed a minimum of 10ms as required or as long as 1s when the LTC3589 is reset using its pushbutton controller. PXA16X Armada Processor Support LTC3589 includes spare register bits that can be accessed by the processor for setting and recalling hibernate and resume operation. The keep-alive function allow a step-down switching regulator to maintain system memory during a hibernate shutdown state of the Armada processor. i.MX Processor Support The LTC3589 has hardware features specifically designed for the latest i.MX family of processors from Freescale Semiconductor. The i.MX37 controls the VSTB input pin of the LTC3589 to command transitions between the run mode core voltage and the lower level standby voltage. The run and standby voltage levels are initially programmed in I2C command registers xxBTV1 and xxBTV2. When the VSTB pin is asserted high all four dynamically controlled output supply rails will slew to the xxBTV2 set point. When xxBTV1 and xxBTV2 are set at the same value, as they are by default, then no slewing occurs. This allows the single VSTB pin to control any combination of the four DAC controlled regulators to slew between two programmed output voltages. When VSTB is de-asserted back to a zero value the regulators slew back up to the xxBTV1 set point. Earlier i.MX family processors such as the i.MX31 included two VSTB pins used for controlling the regulator outputs for a low voltage standby mode, nominal voltage run mode, and a higher voltage overdrive mode. The LTC3589 can be used with these processors using the VSTB input pin
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LTC3589 APPLICATIONS INFORMATION
to select between run and standby voltages and using minimal software overhead to set the overdrive voltage in I2C command registers. The default DAC reference levels in all xxBTVx registers is 0x19. This accommodates i.MX processors and others requiring an overdrive voltage. The voltage can be increased up to 0x1F for overdrive or supply margining above the nominal run voltage. Once programmed into the I2C command registers xxBTVx two voltage outputs are selected by the VSTB pin. All voltage levels and changes are fully controlled using the I2C serial port. OMAP3 and DaVinci Processor Support The OMAP3 family of ARM processors has similar requirements to the processors described above. The LTC3589 I2C control can fully accommodate the smart reflex dynamic voltage control with proper embedded software drivers tailored to the LTC3589 register mapping. The LTC3589 demo board demonstrates configuring and dynamically slewing and sequencing the outputs using I2C control. The same provisions can be incorporated into embedded software drivers for the OMAP3 or any other target processor.
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LTC3589 TYPICAL APPLICATION
10F VIN 10F PVIN1 6 VCORE 0.647V TO 1.34V 1.6A 604K LDO1_STDBY BUCK1_FB 39 10F LDO1_FB LTC3589 PVIN2 24 1.5H 715K VSRAM 9.09k VSOC 10k WAKE 10k PWR_ON 18.2k 10k 10 11 13 14 9 18 20 EN1 EN2 EN3 EN4 EN_LDO2 EN_LDO34 PWR_ON BUCK2_FB 33 10F PVIN3 27 1.5H 681K BUCK3_FB 34 10F PVIN4 BB_OUT 21 ON BB_FB 40 316k 12 2.7H SW4CD VIN_LDO2 LDO2 19 1 2 604k LDO2_FB 38 768k 1F VIN_LDO34 LDO3 5 3 1F LDO4 4 1F 32 31 SDA 30 SCL 28 VSTB 23 WAKE 22 PBSTAT 29 PGOOD DVDD
17 IRQ 8 RST0
37 VIN
FREESCALE i.MX51 NVCC_SRTC_PDW VCC(CORE) FASTR_ANA FASTR_DIG 768K VSRAM/DDR 1.8V 1A 10pF 22F
SW1 VRTC 1.2V 25mA 1F 36
7
1H 10pF 22F
22F
511k 35
1.02M
SW2
25
NVCC_EMI_DRAM NVCC_CNTL_EMI NVCC_PER2,3,4,6,8,9 NVCC_EMI(NAND+EMI)
422K VSOC 0.676V to 1.4V 1A 10pF 22F
SW3
26
VDDGP
9.09k VCORE
787K VIO 3.3V 1.2A 1M 4.7pF 22F VDDA33 VDD_FUSE NVCC__EMI NVCC_PER13,14
15 16
SW4AB
1F
VMEMORY 0.647V TO 1.34V 250mA VANALOG 1.8V 250mA
VDDA VDD_DIG_PLL_A&B VDD_TVDIG VDD_AVA_PLL_A&B NVCC_IPU
1F
VDD_TVSUPPLY AHVDDRGB VAUX 2.8V 250mA NVCC_DAC NVCC_TV_BACK NVCC_USBPHY NVCC_OSC
PWR_ON
GPIO I2C2_SDA I2C2_SCL PMIC_VSTBY_REQ GPIO GPIO PMIC_RDY GPIO1/IRQ POR_B GND
3589 TA02
GND 41
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LTC3589 PACKAGE DESCRIPTION
UJ Package 40-Lead Plastic QFN (6mm x 6mm)
(Reference LTC DWG # 05-08-1728 Rev O)
0.70 0.05
6.50 0.05 4.42 0.05 5.10 0.05 4.50 0.05 (4 SIDES)
4.42 0.05
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
6.00 0.10 (4 SIDES)
0.75 0.05 R = 0.10 TYP
R = 0.115 TYP
39 40 0.40 0.10 1 PIN 1 NOTCH R = 0.45 OR 0.35 x 45 CHAMFER 2
PIN 1 TOP MARK (SEE NOTE 6)
4.50 REF (4-SIDES)
4.42 0.10
4.42 0.10
(UJ40) QFN REV O 0406
0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC3589 TYPICAL APPLICATION
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LTC3556
LTC3577/ Highly Integrated Portable/ LTC3577-1/ Navigation PMIC LTC3577-3/ LTC3577-4 LTC3586/ Switching USB Power LTC3586-1 Manager with Li-Ion/ Polymer Charger, 1A BuckBoost + Dual Sync Buck Converter + Boost + LDO
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44 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0610 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2010

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